Relocation of reconfigurable modules on Xilinx FPGA
The result's identifiers
Result code in IS VaVaI
<a href="https://www.isvavai.cz/riv?ss=detail&h=RIV%2F46747885%3A24220%2F13%3A%230002863" target="_blank" >RIV/46747885:24220/13:#0002863 - isvavai.cz</a>
Result on the web
<a href="http://apps.webofknowledge.com/full_record.do?product=UA&search_mode=GeneralSearch&qid=9&SID=V2ZZlanTQqUyFdhYYcD&page=1&doc=1" target="_blank" >http://apps.webofknowledge.com/full_record.do?product=UA&search_mode=GeneralSearch&qid=9&SID=V2ZZlanTQqUyFdhYYcD&page=1&doc=1</a>
DOI - Digital Object Identifier
<a href="http://dx.doi.org/10.1109/DDECS.2013.6549812" target="_blank" >10.1109/DDECS.2013.6549812</a>
Alternative languages
Result language
angličtina
Original language name
Relocation of reconfigurable modules on Xilinx FPGA
Original language description
This paper presents a design flow that allows relocation of reconfigurable modules on Xilinx FPGAs using dynamic partial reconfiguration (DPR). Relocation of these modules is performed without requirements of re-implementing the design. The article describes the relocation procedure based on modifications of major address of the partial configuration bitstream. This approach allows using single partial bitstream for multiple areas in FPGA device. It reduces a number of partial bitstreams stored in memory, saves the implementation time and it can increase dependability of the system. The proposed flow is demonstrated on a simple example with multiplier and adder locations mutually exchanged.
Czech name
—
Czech description
—
Classification
Type
D - Article in proceedings
CEP classification
JC - Computer hardware and software
OECD FORD branch
—
Result continuities
Project
<a href="/en/project/LD13019" target="_blank" >LD13019: Improvement in Reliability of Nano-scale circuits</a><br>
Continuities
P - Projekt vyzkumu a vyvoje financovany z verejnych zdroju (s odkazem do CEP)<br>S - Specificky vyzkum na vysokych skolach
Others
Publication year
2013
Confidentiality
S - Úplné a pravdivé údaje o projektu nepodléhají ochraně podle zvláštních právních předpisů
Data specific for result type
Article name in the collection
16th International Symposium on Design and Diagnostics of Electronic Circuits and Systems, DDECS 2013
ISBN
978-1-4673-6135-4
ISSN
—
e-ISSN
—
Number of pages
6
Pages from-to
175 - 180
Publisher name
IEEE, 345 E 47TH ST, NEW YORK, NY 10017 USA
Place of publication
—
Event location
Karlovy Vary; Czech Republic
Event date
Jan 1, 2013
Type of event by nationality
WRD - Celosvětová akce
UT code for WoS article
—