Methodology for Fault Tolerant System Design Based on FPGA Into Limited Redundant Area
The result's identifiers
Result code in IS VaVaI
<a href="https://www.isvavai.cz/riv?ss=detail&h=RIV%2F00216305%3A26230%2F13%3APU106378" target="_blank" >RIV/00216305:26230/13:PU106378 - isvavai.cz</a>
Result on the web
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DOI - Digital Object Identifier
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Alternative languages
Result language
angličtina
Original language name
Methodology for Fault Tolerant System Design Based on FPGA Into Limited Redundant Area
Original language description
The paper presents a methodology of fault tolerant system design into an FPGA with the ability of the transient fault and the permanent fault mitigation. The transient fault mitigation is done by the partial dynamic reconfiguration. The mitigation of a certain number of permanent faults is based on using a specific fault tolerant architecture occupiing less resources than the previosly used one and excluding the faulty part of the FPGA. This inovative technique is based on the precompiled configurations stored in an external memory. To reduce the required space for a partial bitstream the relocation technique is used.
Czech name
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Czech description
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Classification
Type
D - Article in proceedings
CEP classification
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OECD FORD branch
10201 - Computer sciences, information science, bioinformathics (hardware development to be 2.2, social aspect to be 5.8)
Result continuities
Project
Result was created during the realization of more than one project. More information in the Projects tab.
Continuities
P - Projekt vyzkumu a vyvoje financovany z verejnych zdroju (s odkazem do CEP)<br>Z - Vyzkumny zamer (s odkazem do CEZ)<br>S - Specificky vyzkum na vysokych skolach
Others
Publication year
2013
Confidentiality
S - Úplné a pravdivé údaje o projektu nepodléhají ochraně podle zvláštních právních předpisů
Data specific for result type
Article name in the collection
16th Euromicro Conference on Digital System Design: Architectures, Methods and Tools
ISBN
978-0-7695-5074-9
ISSN
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e-ISSN
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Number of pages
8
Pages from-to
227-234
Publisher name
IEEE Computer Society
Place of publication
Santander
Event location
Santander
Event date
Sep 4, 2013
Type of event by nationality
WRD - Celosvětová akce
UT code for WoS article
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