Dependability Analysis of Fault Tolerant Systems Based on Partial Dynamic Reconfiguration Implemented into FPGA
The result's identifiers
Result code in IS VaVaI
<a href="https://www.isvavai.cz/riv?ss=detail&h=RIV%2F00216305%3A26230%2F12%3APU101805" target="_blank" >RIV/00216305:26230/12:PU101805 - isvavai.cz</a>
Result on the web
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DOI - Digital Object Identifier
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Alternative languages
Result language
angličtina
Original language name
Dependability Analysis of Fault Tolerant Systems Based on Partial Dynamic Reconfiguration Implemented into FPGA
Original language description
In this paper, a dependability analysis of fault tolerant systems implemented into the SRAM-based FPGA is presented. The fault tolerant architectures are based on redundancy of functional units associated with a concurrent error detection technique and it uses the principles of partial dynamic reconfiguration as a recovery mechanism from a fault occurrence. Architectures are tested by injecting soft errors into partial bitstream in FPGA by SEU injector and the faults coverage of this architecture is obtained. From faults coverage, the failure rate and repair rate are evaluated. Then, for fault tolerant architecture the Markov dependability models are created and it is demonstrated how the reliability and availability parameters are derived from this model for different configurations of architectures and faulty modules. The reliability analysis results are shown.
Czech name
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Czech description
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Classification
Type
D - Article in proceedings
CEP classification
IN - Informatics
OECD FORD branch
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Result continuities
Project
Result was created during the realization of more than one project. More information in the Projects tab.
Continuities
P - Projekt vyzkumu a vyvoje financovany z verejnych zdroju (s odkazem do CEP)<br>S - Specificky vyzkum na vysokych skolach
Others
Publication year
2012
Confidentiality
S - Úplné a pravdivé údaje o projektu nepodléhají ochraně podle zvláštních právních předpisů
Data specific for result type
Article name in the collection
15th Euromicro Conference on Digital System Design: Architectures, Methods and Tools
ISBN
978-0-7695-4798-5
ISSN
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e-ISSN
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Number of pages
8
Pages from-to
250-257
Publisher name
IEEE Computer Society
Place of publication
Cesme-Izmir
Event location
Izmir
Event date
Sep 5, 2012
Type of event by nationality
WRD - Celosvětová akce
UT code for WoS article
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