Introduction to Fixed-point Multiplication and Signal Processing Application
Result description
The contribution deals with a binary representation of integer and real numbers. In domain of digital signal processing the number representation is either in fixed-point or floating-point form. In the text the algorithm for unsigned binary multiplication for fixed-point representation is presented. There are many processors with fixed or floating-point representation and there are also several blocks used for arithmetical operations in FPGA. But generally these blocks do not have a large variability interms of bit width. The goal of the contribution is mainly to present an arithmetical model and to evaluate its complexity for a large number of possible implemented algorithms. For testing of product algorithm the multidimensional convolution of gray scale images was performed as well.
Keywords
Digital arithmeticFixed point arithmeticMultiplicationMultidimensional signal processing
The result's identifiers
Result code in IS VaVaI
Result on the web
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DOI - Digital Object Identifier
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Alternative languages
Result language
angličtina
Original language name
Introduction to Fixed-point Multiplication and Signal Processing Application
Original language description
The contribution deals with a binary representation of integer and real numbers. In domain of digital signal processing the number representation is either in fixed-point or floating-point form. In the text the algorithm for unsigned binary multiplication for fixed-point representation is presented. There are many processors with fixed or floating-point representation and there are also several blocks used for arithmetical operations in FPGA. But generally these blocks do not have a large variability interms of bit width. The goal of the contribution is mainly to present an arithmetical model and to evaluate its complexity for a large number of possible implemented algorithms. For testing of product algorithm the multidimensional convolution of gray scale images was performed as well.
Czech name
Introduction to Fixed-point Multiplication and Signal Processing Application
Czech description
The contribution deals with a binary representation of integer and real numbers. In domain of digital signal processing the number representation is either in fixed-point or floating-point form. In the text the algorithm for unsigned binary multiplication for fixed-point representation is presented. There are many processors with fixed or floating-point representation and there are also several blocks used for arithmetical operations in FPGA. But generally these blocks do not have a large variability interms of bit width. The goal of the contribution is mainly to present an arithmetical model and to evaluate its complexity for a large number of possible implemented algorithms. For testing of product algorithm the multidimensional convolution of gray scale images was performed as well.
Classification
Type
D - Article in proceedings
CEP classification
JA - Electronics and optoelectronics
OECD FORD branch
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Result continuities
Project
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Continuities
Z - Vyzkumny zamer (s odkazem do CEZ)
Others
Publication year
2009
Confidentiality
S - Úplné a pravdivé údaje o projektu nepodléhají ochraně podle zvláštních právních předpisů
Data specific for result type
Article name in the collection
Proceedings of 19th International Conference Radioelektronika 2009
ISBN
978-1-4244-3536-4
ISSN
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e-ISSN
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Number of pages
4
Pages from-to
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Publisher name
Neuveden
Place of publication
Bratislava (Slovakia)
Event location
Institute for Public Administration
Event date
Apr 22, 2009
Type of event by nationality
EUR - Evropská akce
UT code for WoS article
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Result type
D - Article in proceedings
CEP
JA - Electronics and optoelectronics
Year of implementation
2009