Optimization of oversampling Data Recovery

Result code in IS VaVaI

<a href="https://www.isvavai.cz/riv?ss=detail&h=RIV%2F00216305%3A26220%2F09%3APU82205" target="_blank" >RIV/00216305:26220/09:PU82205 - isvavai.cz</a>

Alternative codes found

RIV/60162694:G43__/09:#0003131

Result on the web

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DOI - Digital Object Identifier

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Result language

čeština

Original language name

Optimization of oversampling Data Recovery

Original language description

The paper deals with the design and optimization of blind oversampling clock and data recovery (CDR) based on FPGA prototyping. The main advantage of the oversampling CDR is the fully digital architecture, which enables the FPGA-based testing and its subsequent integration into any ASIC technology. The oversampling CDR is a promising block for free space optical (FSO) applications because of its extremely short reacquisition time, which is the key feature for efficient communication over the frequentlyfading channel. An efficient statistical simulation model for the CDR optimization is presented. Our effort in optimization was focused mainly on the simplification of the decision algorithm while maintaining acceptable jitter tolerance. The suggested method was verified on the Xilinx FPGA platform.

Czech name

Optimization of oversampling Data Recovery

Czech description

The paper deals with the design and optimization of blind oversampling clock and data recovery (CDR) based on FPGA prototyping. The main advantage of the oversampling CDR is the fully digital architecture, which enables the FPGA-based testing and its subsequent integration into any ASIC technology. The oversampling CDR is a promising block for free space optical (FSO) applications because of its extremely short reacquisition time, which is the key feature for efficient communication over the frequentlyfading channel. An efficient statistical simulation model for the CDR optimization is presented. Our effort in optimization was focused mainly on the simplification of the decision algorithm while maintaining acceptable jitter tolerance. The suggested method was verified on the Xilinx FPGA platform.

Type

D - Article in proceedings

CEP classification

JA - Electronics and optoelectronics

OECD FORD branch

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Project

Result was created during the realization of more than one project. More information in the Projects tab.

Continuities

P - Projekt vyzkumu a vyvoje financovany z verejnych zdroju (s odkazem do CEP)<br>Z - Vyzkumny zamer (s odkazem do CEZ)

Publication year

2009

Confidentiality

S - Úplné a pravdivé údaje o projektu nepodléhají ochraně podle zvláštních právních předpisů

Article name in the collection

Circuits and Systems, 2009. MWSCAS '09. 52nd IEEE International Midwest Symposium on

ISBN

978-1-4244-4479-3

ISSN

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e-ISSN

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Number of pages

4

Pages from-to

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Publisher name

IEEE

Place of publication

Mexico

Event location

Cancun, Mexico

Event date

Aug 2, 2009

Type of event by nationality

WRD - Celosvětová akce

UT code for WoS article

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