FPGA-based In-system Jitter Measurement

Result code in IS VaVaI
<a href="https://www.isvavai.cz/riv?ss=detail&h=RIV%2F00216305%3A26220%2F11%3APU94769" target="_blank" >RIV/00216305:26220/11:PU94769 - isvavai.cz</a>
Result on the web
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DOI - Digital Object Identifier
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Result language
angličtina
Original language name
FPGA-based In-system Jitter Measurement
Original language description
The paper presents a simple jitter measurement device implemented in FPGA. The device for the jitter measurement is closely coupled with a blind oversampling data recovery circuit (BO-CDR), which is sometimes used in asynchronous high speed data receivers as an alternative to the traditional PLL-based CDR circuit. The jitter measurement itself is based on estimating the edge density distribution over one unit interval via evaluating the number of detected edges in particular time intervals. The method enables simultaneous data transmission and real-time signal quality estimation without affecting the data signal, which is probably the main benefit of the proposed solution. There is no need for any additional hardware except the FPGA. The jitter evaluation is done completely within the gate array, requiring a few of its hardware resources. The proposed device was successfully implemented and tested on an optical data link. Real measurement results are presented together with reference m
Czech name
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Czech description
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Project
Result was created during the realization of more than one project. More information in the Projects tab.
Continuities
P - Projekt vyzkumu a vyvoje financovany z verejnych zdroju (s odkazem do CEP)<br>Z - Vyzkumny zamer (s odkazem do CEZ)

Publication year
2011
Confidentiality
S - Úplné a pravdivé údaje o projektu nepodléhají ochraně podle zvláštních právních předpisů

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