Blind Oversampling Data Recovery with Low Hardware Complexity

Result code in IS VaVaI

<a href="https://www.isvavai.cz/riv?ss=detail&h=RIV%2F00216305%3A26220%2F10%3APU86403" target="_blank" >RIV/00216305:26220/10:PU86403 - isvavai.cz</a>

Result on the web

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DOI - Digital Object Identifier

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Result language

angličtina

Original language name

Blind Oversampling Data Recovery with Low Hardware Complexity

Original language description

The paper is focused on the optimization and implementation of fully digital feed-forward blind oversampling CDR (BO-CDR). Two new phase-decision algorithms are proposed. Their complexity is very low, enabling a very simple and fast implementation even in FPGA, which was used as a development platform as well as a target device for the BO-CDR block. The FPGA-based optimization gave the opportunity to perform on-the-fly optimization under real conditions of target link. This greatly shortened the development time as there were no errors caused by inaccurate simulation models. Measurement results obtained on real links are included showing the jitter tolerance of the proposed algorithms to be comparable to the performance of modern PLL-based CDRs.

Czech name

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Czech description

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Type

J_x - Unclassified - Peer-reviewed scientific article (Jimp, Jsc and Jost)

CEP classification

JA - Electronics and optoelectronics

OECD FORD branch

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Project

Result was created during the realization of more than one project. More information in the Projects tab.

Continuities

Z - Vyzkumny zamer (s odkazem do CEZ)

Publication year

2010

Confidentiality

S - Úplné a pravdivé údaje o projektu nepodléhají ochraně podle zvláštních právních předpisů

Name of the periodical

Radioengineering

ISSN

1210-2512

e-ISSN

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Volume of the periodical

2010

Issue of the periodical within the volume

1

Country of publishing house

CZ - CZECH REPUBLIC

Number of pages

5

Pages from-to

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UT code for WoS article

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EID of the result in the Scopus database

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