In-System Jitter Measurement Using FPGA

Result code in IS VaVaI
<a href="https://www.isvavai.cz/riv?ss=detail&h=RIV%2F00216305%3A26220%2F10%3APU92199" target="_blank" >RIV/00216305:26220/10:PU92199 - isvavai.cz</a>
Result on the web
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DOI - Digital Object Identifier
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Result language
angličtina
Original language name
In-System Jitter Measurement Using FPGA
Original language description
The paper describes architecture, detailed implementation and measurement results of newly developed jitter measurement device. The device is implemented using a single FPGA. Probably the biggest benefit of the proposed method is that it requires no external components, just the FPGA. As such it can be implemented into an existing receiver with an FPGA without any changes to its hardware. The new jitter measurement block was implementer and tested on a real link. Comparison with jitter measurement usingan oscilloscope is given to prove its reasonable performance. Compared to previously published jitter measurement methods the module is able to monitor high frequency jitter. It is also very efficient in terms of required hardware resources.
Czech name
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Czech description
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Project
Result was created during the realization of more than one project. More information in the Projects tab.
Continuities
Z - Vyzkumny zamer (s odkazem do CEZ)<br>S - Specificky vyzkum na vysokych skolach<br>R - Projekt Ramcoveho programu EK

Publication year
2010
Confidentiality
S - Úplné a pravdivé údaje o projektu nepodléhají ochraně podle zvláštních právních předpisů

Article name in the collection
Proceedings of 20th International Conference Radioelektronika 2010
ISBN
978-1-4244-6319-0
ISSN
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e-ISSN
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Number of pages
4
Pages from-to
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Publisher name
Department of Radio Electronics, Brno University of Technology
Place of publication
Brno, Česká republika, Vysoké učení technic
Event location
Brno
Event date
Apr 19, 2010
Type of event by nationality
WRD - Celosvětová akce
UT code for WoS article
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