IMPROVED DESIGN FOR MODULO 2n+1 ADDER
The result's identifiers
Result code in IS VaVaI
<a href="https://www.isvavai.cz/riv?ss=detail&h=RIV%2F00216305%3A26220%2F10%3APU87910" target="_blank" >RIV/00216305:26220/10:PU87910 - isvavai.cz</a>
Result on the web
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DOI - Digital Object Identifier
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Alternative languages
Result language
angličtina
Original language name
IMPROVED DESIGN FOR MODULO 2n+1 ADDER
Original language description
2n + 1 modular adders are widely used in Residue Number System arithmetic. Their performance is restricted due to the hardware implementation complexity. In this paper a novel circuit design for 2n + 1 adder has been proposed. This design reduces the bitlength of operands used in most 2n + 1 residue adders from (n+1) to n bit long. Thereby complexity of VLSI implementation and delay of the overall system will be reduced. The proposed circuit has been implemented using VHDL to prove the theoretical consideration.
Czech name
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Czech description
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Classification
Type
D - Article in proceedings
CEP classification
JA - Electronics and optoelectronics
OECD FORD branch
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Result continuities
Project
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Continuities
Z - Vyzkumny zamer (s odkazem do CEZ)
Others
Publication year
2010
Confidentiality
S - Úplné a pravdivé údaje o projektu nepodléhají ochraně podle zvláštních právních předpisů
Data specific for result type
Article name in the collection
Electronic Devices and Systems IMAPS CS International Conference 2010
ISBN
978-80-214-4138-5
ISSN
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e-ISSN
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Number of pages
3
Pages from-to
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Publisher name
Neuveden
Place of publication
Brno
Event location
Brno
Event date
Sep 1, 2010
Type of event by nationality
WRD - Celosvětová akce
UT code for WoS article
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