NOVEL ARCHITECTURES OF MODULO 2n +/- 1 ADDERS FOR FIELD PROGRAMMABLE GATE ARRAY
The result's identifiers
Result code in IS VaVaI
<a href="https://www.isvavai.cz/riv?ss=detail&h=RIV%2F00216305%3A26220%2F11%3APU92930" target="_blank" >RIV/00216305:26220/11:PU92930 - isvavai.cz</a>
Result on the web
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DOI - Digital Object Identifier
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Alternative languages
Result language
angličtina
Original language name
NOVEL ARCHITECTURES OF MODULO 2n +/- 1 ADDERS FOR FIELD PROGRAMMABLE GATE ARRAY
Original language description
This paper presents two new architectures of residue number system adders for moduli 2n-1, 2n+1. These two architectures allow efficient implementation on Field Programmable Gate Array (FPGA). Both designs depend on prefix carry computation, in order tospeed up the computation time and get rid of the necessity to a second adder; the commonly used structure. Carry ripple adders (CRA) were used in this paper due to the dedicated carry ripple logic built-in FPGAs. The proposed designs were implemented onSpartan-3 xc3s200-ft256-4 FPGA. A comparison with published designs was done in terms of time and area consumption and showed time savings up to 44.7 %.
Czech name
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Czech description
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Classification
Type
D - Article in proceedings
CEP classification
JA - Electronics and optoelectronics
OECD FORD branch
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Result continuities
Project
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Continuities
Z - Vyzkumny zamer (s odkazem do CEZ)
Others
Publication year
2011
Confidentiality
S - Úplné a pravdivé údaje o projektu nepodléhají ochraně podle zvláštních právních předpisů
Data specific for result type
Article name in the collection
IMPAS CS International Conference 2011
ISBN
978-80-214-4303-7
ISSN
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e-ISSN
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Number of pages
6
Pages from-to
51-56
Publisher name
Neuveden
Place of publication
Brno
Event location
Brno
Event date
Jun 22, 2011
Type of event by nationality
WRD - Celosvětová akce
UT code for WoS article
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