TWO MODULO 2n +/- 1 ADDERS BASED ON PREFIX COMPUTATION
The result's identifiers
Result code in IS VaVaI
<a href="https://www.isvavai.cz/riv?ss=detail&h=RIV%2F00216305%3A26220%2F11%3APU96361" target="_blank" >RIV/00216305:26220/11:PU96361 - isvavai.cz</a>
Result on the web
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DOI - Digital Object Identifier
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Alternative languages
Result language
angličtina
Original language name
TWO MODULO 2n +/- 1 ADDERS BASED ON PREFIX COMPUTATION
Original language description
Two novel designs of residue number system adders corresponding moduli 2n?1, 2n+1 are presented in this paper. Both designs are based on prefix computation idea, which was inspired from the technique used in carry look-ahead adder (CLA). This prefix computation speeds up the addition-correction process corresponding to each modulo. The proposed modular adders were designed in such a way to be efficiently implemented on Spartan-3 field programmable gate array (FPGA) board. The implementation results showed time, area savings up to 44.7%, 14.3%, respectively, which indicates that these adders are very effective for designs with critical timing requirements.
Czech name
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Czech description
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Classification
Type
D - Article in proceedings
CEP classification
JA - Electronics and optoelectronics
OECD FORD branch
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Result continuities
Project
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Continuities
Z - Vyzkumny zamer (s odkazem do CEZ)
Others
Publication year
2011
Confidentiality
S - Úplné a pravdivé údaje o projektu nepodléhají ochraně podle zvláštních právních předpisů
Data specific for result type
Article name in the collection
IMAPS - Mikroelektronika současnosti
ISBN
978-80-214-4404-1
ISSN
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e-ISSN
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Number of pages
6
Pages from-to
1-6
Publisher name
Neuveden
Place of publication
Neuveden
Event location
Horní Bečva
Event date
May 19, 2011
Type of event by nationality
CST - Celostátní akce
UT code for WoS article
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