Analysis of Non-ideal Effects of Pipelined ADC by Using MATLAB - Simulink

Result code in IS VaVaI
<a href="https://www.isvavai.cz/riv?ss=detail&h=RIV%2F00216305%3A26220%2F10%3APU88748" target="_blank" >RIV/00216305:26220/10:PU88748 - isvavai.cz</a>
Result on the web
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DOI - Digital Object Identifier
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Result language
čeština
Original language name
Analysis of Non-ideal Effects of Pipelined ADC by Using MATLAB - Simulink
Original language description
The presented work deals with analysis of non-ideal effect of pipelined analog-to-digital converter (ADC) such as random capacitor mismatch, comparator offset and finite op-amp gain. These factors arise during a conversion in the pipelined ADC when usingCMOS technology and switched-capacitors (SC) technique. The pipelined ADC was simulated in MATLAB-Simulink simulation environment.
Czech name
Analysis of Non-ideal Effects of Pipelined ADC by Using MATLAB - Simulink
Czech description
The presented work deals with analysis of non-ideal effect of pipelined analog-to-digital converter (ADC) such as random capacitor mismatch, comparator offset and finite op-amp gain. These factors arise during a conversion in the pipelined ADC when usingCMOS technology and switched-capacitors (SC) technique. The pipelined ADC was simulated in MATLAB-Simulink simulation environment.

Project
<a href="/en/project/GA102%2F09%2F1628" target="_blank" >GA102/09/1628: Research and development of digitally controlled integrated mixed-mode circuits</a><br>
Continuities
Z - Vyzkumny zamer (s odkazem do CEZ)<br>S - Specificky vyzkum na vysokych skolach

Publication year
2010
Confidentiality
S - Úplné a pravdivé údaje o projektu nepodléhají ochraně podle zvláštních právních předpisů

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