Pipelined ADC Design Requirements
The result's identifiers
Result code in IS VaVaI
<a href="https://www.isvavai.cz/riv?ss=detail&h=RIV%2F00216305%3A26220%2F11%3APU92080" target="_blank" >RIV/00216305:26220/11:PU92080 - isvavai.cz</a>
Result on the web
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DOI - Digital Object Identifier
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Alternative languages
Result language
angličtina
Original language name
Pipelined ADC Design Requirements
Original language description
The presented work deals with design and analysis of a pipelined analog-to-digital converter (ADC). There exist error sources such as finite DC gain of opamp, capacitor mismatch, opamp bandwidth, etc., arising when the switched capacitor (SC) technique and CMOS technology are used. These error sources are explained and their influences on overall parameters of the pipelined ADC are studied. The pipelined ADC was simulated in MATLAB-Simulink and CADENCE simulation environment.
Czech name
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Czech description
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Classification
Type
D - Article in proceedings
CEP classification
JA - Electronics and optoelectronics
OECD FORD branch
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Result continuities
Project
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Continuities
S - Specificky vyzkum na vysokych skolach
Others
Publication year
2011
Confidentiality
S - Úplné a pravdivé údaje o projektu nepodléhají ochraně podle zvláštních právních předpisů
Data specific for result type
Article name in the collection
Proceedings of the 17th Conference STUDENT EEICT 2011
ISBN
978-80-214-4273-3
ISSN
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e-ISSN
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Number of pages
5
Pages from-to
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Publisher name
NOVPRESS s.r.o.
Place of publication
Brno
Event location
Brno
Event date
Apr 28, 2011
Type of event by nationality
CST - Celostátní akce
UT code for WoS article
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