Basic Block of Pipelined ADC Design Requirements

Result code in IS VaVaI

<a href="https://www.isvavai.cz/riv?ss=detail&h=RIV%2F00216305%3A26220%2F11%3APU91861" target="_blank" >RIV/00216305:26220/11:PU91861 - isvavai.cz</a>

Result on the web

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DOI - Digital Object Identifier

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Result language

angličtina

Original language name

Basic Block of Pipelined ADC Design Requirements

Original language description

The paper describes design requirements of a basic stage (called MDAC - Multiplying Digital-to-Analog Converter) of a pipelined ADC. There exist error sources such as finite DC gain of opamp, capacitor mismatch, thermal noise, etc., arising when the switched capacitor (SC) technique and CMOS technology are used. These non-idealities are explained and their influences on overall parameters of a pipelined ADC are studied. The pipelined ADC including non-idealities was modeled in MATLAB - Simulink simulation environment.

Czech name

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Czech description

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Type

J_x - Unclassified - Peer-reviewed scientific article (Jimp, Jsc and Jost)

CEP classification

JA - Electronics and optoelectronics

OECD FORD branch

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Project

<a href="/en/project/GAP102%2F11%2F1379" target="_blank" >GAP102/11/1379: Novel Intelligent Submicron Structures and Microsystems for Advanced Microsensors</a><br>

Continuities

Z - Vyzkumny zamer (s odkazem do CEZ)<br>S - Specificky vyzkum na vysokych skolach

Publication year

2011

Confidentiality

S - Úplné a pravdivé údaje o projektu nepodléhají ochraně podle zvláštních právních předpisů

Name of the periodical

Radioengineering

ISSN

1210-2512

e-ISSN

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Volume of the periodical

2011

Issue of the periodical within the volume

1

Country of publishing house

CZ - CZECH REPUBLIC

Number of pages

5

Pages from-to

234-238

UT code for WoS article

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EID of the result in the Scopus database

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