Serial IIR Filter Generator for ASIC
The result's identifiers
Result code in IS VaVaI
<a href="https://www.isvavai.cz/riv?ss=detail&h=RIV%2F00216305%3A26220%2F12%3APU99676" target="_blank" >RIV/00216305:26220/12:PU99676 - isvavai.cz</a>
Result on the web
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DOI - Digital Object Identifier
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Alternative languages
Result language
angličtina
Original language name
Serial IIR Filter Generator for ASIC
Original language description
The paper presents an infinite impulse response (IIR) filter generator for application specific integration circuits (ASICs). The paper describes the filter architecture with serial calculation. This architecture utilizes one shared multiply and accumulate (MAC) unit in order to achieve minimal area on chip. A software in C++ language for automatic filter generation was written. The software generates fully synthesizable VHDL description of filter, batch file for simulator and test-bench file for filterverification from the filter specification file.
Czech name
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Czech description
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Classification
Type
D - Article in proceedings
CEP classification
JA - Electronics and optoelectronics
OECD FORD branch
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Result continuities
Project
<a href="/en/project/GAP102%2F11%2F1379" target="_blank" >GAP102/11/1379: Novel Intelligent Submicron Structures and Microsystems for Advanced Microsensors</a><br>
Continuities
S - Specificky vyzkum na vysokych skolach
Others
Publication year
2012
Confidentiality
S - Úplné a pravdivé údaje o projektu nepodléhají ochraně podle zvláštních právních předpisů
Data specific for result type
Article name in the collection
Electronic Devices and Systems IMAPS CS International Conference 2011 Proceedings
ISBN
978-80-214-4539-0
ISSN
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e-ISSN
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Number of pages
5
Pages from-to
219-223
Publisher name
Vysoké učení technické v Brně
Place of publication
Brno
Event location
Brno
Event date
Jun 28, 2012
Type of event by nationality
WRD - Celosvětová akce
UT code for WoS article
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