Serial IIR Filter Structure Generator for ASICs

Result code in IS VaVaI

<a href="https://www.isvavai.cz/riv?ss=detail&h=RIV%2F00216305%3A26220%2F12%3APU101422" target="_blank" >RIV/00216305:26220/12:PU101422 - isvavai.cz</a>

Result on the web

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DOI - Digital Object Identifier

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Result language

angličtina

Original language name

Serial IIR Filter Structure Generator for ASICs

Original language description

The paper presents generator of an infinite impulse response (IIR) digital filter structure for implementation in application specific integration circuits (ASICs). The paper describes the filter architecture with serial calculation. The serial architecture utilizes one shared multiply and accumulate (MAC) unit in order to achieve minimal area on chip. Software in C++ language was written for automatic filter generation. The software generates fully synthesizable VHDL description of filter, batch file for simulator and test-bench file for automatic filter verification from the filter specification file.

Czech name

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Czech description

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Type

J_x - Unclassified - Peer-reviewed scientific article (Jimp, Jsc and Jost)

CEP classification

JA - Electronics and optoelectronics

OECD FORD branch

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Project

<a href="/en/project/GAP102%2F11%2F1379" target="_blank" >GAP102/11/1379: Novel Intelligent Submicron Structures and Microsystems for Advanced Microsensors</a><br>

Continuities

S - Specificky vyzkum na vysokych skolach

Publication year

2012

Confidentiality

S - Úplné a pravdivé údaje o projektu nepodléhají ochraně podle zvláštních právních předpisů

Name of the periodical

ElectroScope - http://www.electroscope.zcu.cz

ISSN

1802-4564

e-ISSN

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Volume of the periodical

2012

Issue of the periodical within the volume

6

Country of publishing house

CZ - CZECH REPUBLIC

Number of pages

4

Pages from-to

1-4

UT code for WoS article

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EID of the result in the Scopus database

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