Optimized Architecture of High Order CIC Filters

Result code in IS VaVaI
<a href="https://www.isvavai.cz/riv?ss=detail&h=RIV%2F00216305%3A26220%2F13%3APU104617" target="_blank" >RIV/00216305:26220/13:PU104617 - isvavai.cz</a>
Result on the web
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DOI - Digital Object Identifier
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Result language
angličtina
Original language name
Optimized Architecture of High Order CIC Filters
Original language description
The paper presents an optimized architecture of cascaded integrator-comb (CIC) digital filter structure. The structure is suitable for implementation in application specific integration circuits (ASICs) or field programmable gate arrays (FPGAs). The mainadvantages of the architecture are higher working frequency, smaller area size and lower power consumption. Software in C++ language was written for automatic filter generation. The software generates fully synthesizable VHDL description of filter, batch file for simulator and test-bench file for automatic filter verification from the filter specification file.
Czech name
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Czech description
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Project
Result was created during the realization of more than one project. More information in the Projects tab.
Continuities
P - Projekt vyzkumu a vyvoje financovany z verejnych zdroju (s odkazem do CEP)<br>S - Specificky vyzkum na vysokych skolach

Publication year
2013
Confidentiality
S - Úplné a pravdivé údaje o projektu nepodléhají ochraně podle zvláštních právních předpisů

Article name in the collection
Proceedings of the 20th International Conference Mixed Design of Integrated Circuits and Systems
ISBN
978-83-63578-01-5
ISSN
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e-ISSN
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Number of pages
4
Pages from-to
263-266
Publisher name
Lodz University of Technology
Place of publication
Lodz, Poland
Event location
Gdynia
Event date
Jun 20, 2013
Type of event by nationality
WRD - Celosvětová akce
UT code for WoS article
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