Low Level Source Code Optimizing for Single/Multi/core Digital Signal Processors

Result code in IS VaVaI
<a href="https://www.isvavai.cz/riv?ss=detail&h=RIV%2F00216305%3A26220%2F13%3APU104160" target="_blank" >RIV/00216305:26220/13:PU104160 - isvavai.cz</a>
Result on the web
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DOI - Digital Object Identifier
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Result language
angličtina
Original language name
Low Level Source Code Optimizing for Single/Multi/core Digital Signal Processors
Original language description
Paper presents the optimized implementation of the digital signal processing algorithms (real and complex Fast Fourier Transforms) for the specific hardware architecture. The algorithms' source codes were optimized at low level, while all redundant operations (e.g. branching instructions) were avoided. Contrary to results compiled from the high level codes, time consuming load/store operations were considerably eliminated as well and temporal data were stored in the general purpose registers. Contrary to other implementations, the several calls of the identical functions (but with shared data) provide a~reducing of the processor idle states. The TMS320C6748 and TMS320C6678 digital signal processors with the Very Long Instruction Word architecture were used for the implementation of proposed functions. The average duration of FFT optimized functions is between five CPU cycles for four real values and 44 CPU cycles for sixteen real values, respectively.
Czech name
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Czech description
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Project
Result was created during the realization of more than one project. More information in the Projects tab.
Continuities
P - Projekt vyzkumu a vyvoje financovany z verejnych zdroju (s odkazem do CEP)<br>S - Specificky vyzkum na vysokych skolach

Publication year
2013
Confidentiality
S - Úplné a pravdivé údaje o projektu nepodléhají ochraně podle zvláštních právních předpisů

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