Comparative study of Sub-volt Differential Difference Current Conveyors

Result code in IS VaVaI
<a href="https://www.isvavai.cz/riv?ss=detail&h=RIV%2F00216305%3A26220%2F13%3APU104629" target="_blank" >RIV/00216305:26220/13:PU104629 - isvavai.cz</a>
Result on the web
<a href="http://dx.doi.org/10.1016/j.mejo.2013.08.015" target="_blank" >http://dx.doi.org/10.1016/j.mejo.2013.08.015</a>
DOI - Digital Object Identifier
<a href="http://dx.doi.org/10.1016/j.mejo.2013.08.015" target="_blank" >10.1016/j.mejo.2013.08.015</a>

Result language
angličtina
Original language name
Comparative study of Sub-volt Differential Difference Current Conveyors
Original language description
Enhancing the performances of analog circuits with sub-volt supplies becomes a great challenge for circuit designers. Techniques such as bulk-driven (BD) and quasi-floating gate (QFG) count among the suitable ones for ultra-low voltage (ULV) operation capability with extended input voltage range and simple CMOS circuitry. However, in comparison to the conventional gate-driven (GD) MOS transistor (MOST), these techniques suffer from several disadvantages such as low transconductance value and bandwidth that limits their applicability for some applications. Therefore, the idea of merging the BD and QFG techniques to eliminate their drawbacks appears as efficacious solution. This new merging is named bulk-driven quasi-floating gate (BD-QFG) technique and in order to demonstrate its advantages in compassion to BD and QFG ones, this paper presents a comparison study of three ULV differential difference current conveyor (DDCC) blocks based on BD, QFG and BD-QFG techniques. The significant increment of the transconductance and the bandwidth values of the BD-QFG are clearly observed. The proposed CMOS structures of the DDCCs work at +-300 mV supply voltage and 18.5 uW power consumption. The simulation results using 0.18 um CMOS n-Well process from TSMC show the features of the proposed circuits.
Czech name
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Czech description
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Type
J<sub>x</sub> - Unclassified - Peer-reviewed scientific article (Jimp, Jsc and Jost)
CEP classification
JA - Electronics and optoelectronics
OECD FORD branch
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Project
Result was created during the realization of more than one project. More information in the Projects tab.
Continuities
P - Projekt vyzkumu a vyvoje financovany z verejnych zdroju (s odkazem do CEP)

Publication year
2013
Confidentiality
S - Úplné a pravdivé údaje o projektu nepodléhají ochraně podle zvláštních právních předpisů

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