Bulk-driven floating-gate and bulk-driven quasi-floating-gate techniques for low-voltage low-power analog circuits design
The result's identifiers
Result code in IS VaVaI
<a href="https://www.isvavai.cz/riv?ss=detail&h=RIV%2F00216305%3A26220%2F14%3APU104661" target="_blank" >RIV/00216305:26220/14:PU104661 - isvavai.cz</a>
Result on the web
<a href="http://dx.doi.org/10.1016/j.aeue.2013.08.019" target="_blank" >http://dx.doi.org/10.1016/j.aeue.2013.08.019</a>
DOI - Digital Object Identifier
<a href="http://dx.doi.org/10.1016/j.aeue.2013.08.019" target="_blank" >10.1016/j.aeue.2013.08.019</a>
Alternative languages
Result language
angličtina
Original language name
Bulk-driven floating-gate and bulk-driven quasi-floating-gate techniques for low-voltage low-power analog circuits design
Original language description
In this paper, novel non-conventional techniques, named by the author of this paper "bulk-driven floating-gate (BD-FG)" MOS transistor (MOST) and "bulk-driven quasi-floating-gate (BD-QFG) MOST" for low-voltage (LV) low-power (LP) analog circuit design are presented. These novel techniques appear as a good solution to merge the advantages of floating-gate (FG) and quasi-floating-gate (QFG) with the advantages of bulk-driven (BD) technique and suppress their disadvantages. Consequently, the transconductance and transient frequency of BD-FG and BD-QFG MOSTs approach the conventional gate driven (GD) MOST values. Furthermore, a novel LV LP class AB second generation current conveyor based on BD-FG MOST is presented in this paper as an example. The supply voltage is only +-0.4 V with a rail-to-rail voltage swing capability and total power consumption of mere 10 uW. PSpice simulation results using the 0.18 um P-well CMOS technology are included to confirm the attractive properties of these new techniques.
Czech name
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Czech description
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Classification
Type
J<sub>imp</sub> - Article in a specialist periodical, which is included in the Web of Science database
CEP classification
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OECD FORD branch
20201 - Electrical and electronic engineering
Result continuities
Project
Result was created during the realization of more than one project. More information in the Projects tab.
Continuities
P - Projekt vyzkumu a vyvoje financovany z verejnych zdroju (s odkazem do CEP)
Others
Publication year
2014
Confidentiality
S - Úplné a pravdivé údaje o projektu nepodléhají ochraně podle zvláštních právních předpisů
Data specific for result type
Name of the periodical
AEU - International Journal of Electronics and Communications
ISSN
1434-8411
e-ISSN
1618-0399
Volume of the periodical
2014 (68)
Issue of the periodical within the volume
1, IF: 0.696
Country of publishing house
DE - GERMANY
Number of pages
9
Pages from-to
64-72
UT code for WoS article
000328795600010
EID of the result in the Scopus database
2-s2.0-84887471881