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Resistorless Electronically Tunable Grounded Inductance Simulator Design

The result's identifiers

  • Result code in IS VaVaI

    <a href="https://www.isvavai.cz/riv?ss=detail&h=RIV%2F00216305%3A26220%2F17%3APU124283" target="_blank" >RIV/00216305:26220/17:PU124283 - isvavai.cz</a>

  • Result on the web

    <a href="http://ieeexplore.ieee.org/document/8075987/" target="_blank" >http://ieeexplore.ieee.org/document/8075987/</a>

  • DOI - Digital Object Identifier

    <a href="http://dx.doi.org/10.1109/TSP.2017.8075987" target="_blank" >10.1109/TSP.2017.8075987</a>

Alternative languages

  • Result language

    angličtina

  • Original language name

    Resistorless Electronically Tunable Grounded Inductance Simulator Design

  • Original language description

    A new realization of grounded lossless positive inductance simulator (PIS) using simple inverting voltage buffer and unity-gain current follower/inverter (CF±) is reported. Considering the input intrinsic resistance of CF± as useful active parameter, the proposed PIS can be considered as resistorless circuit and it only employs in total 16 Metal-Oxide-Semiconductor (MOS) transistors and a grounded capacitor. The resulting equivalent inductance value of the proposed simulator can be adjusted via change of input intrinsic resistance of CF± by means of its supply voltages. The behavior of the proposed simulator circuit is tested via implementation in voltage-mode 5th-order high-pass filter RLC prototype with Bessel, Butterworth, and Chebyshev I approximation. Theoretical results are verified by SPICE simulations using TSMC 0.18 μm level-7 LO EPI SCN018 CMOS process parameters with ±0.9 V supply voltages.

  • Czech name

  • Czech description

Classification

  • Type

    D - Article in proceedings

  • CEP classification

  • OECD FORD branch

    20201 - Electrical and electronic engineering

Result continuities

  • Project

    Result was created during the realization of more than one project. More information in the Projects tab.

  • Continuities

    P - Projekt vyzkumu a vyvoje financovany z verejnych zdroju (s odkazem do CEP)

Others

  • Publication year

    2017

  • Confidentiality

    S - Úplné a pravdivé údaje o projektu nepodléhají ochraně podle zvláštních právních předpisů

Data specific for result type

  • Article name in the collection

    Proceedings of the 2017 40th International Conference on Telecommunications and Signal Processing (TSP)

  • ISBN

    978-1-5090-3982-1

  • ISSN

  • e-ISSN

  • Number of pages

    4

  • Pages from-to

    279-282

  • Publisher name

    IEEE

  • Place of publication

    Barcelona, Spain

  • Event location

    Barcelona

  • Event date

    Jul 5, 2017

  • Type of event by nationality

    WRD - Celosvětová akce

  • UT code for WoS article

    000425229000061