CMOS Bi-directional Ultra-wideband Galvanically Isolated Die-to-die Communication Utilizing a Double-isolated Transformer

Result code in IS VaVaI
<a href="https://www.isvavai.cz/riv?ss=detail&h=RIV%2F00216305%3A26220%2F18%3APU134690" target="_blank" >RIV/00216305:26220/18:PU134690 - isvavai.cz</a>
Result on the web
<a href="https://ieeexplore.ieee.org/document/8393609" target="_blank" >https://ieeexplore.ieee.org/document/8393609</a>
DOI - Digital Object Identifier
<a href="http://dx.doi.org/10.1109/ISPSD.2018.8393609" target="_blank" >10.1109/ISPSD.2018.8393609</a>

Result language
angličtina
Original language name
CMOS Bi-directional Ultra-wideband Galvanically Isolated Die-to-die Communication Utilizing a Double-isolated Transformer
Original language description
In this work, an ultra-wideband (UWB) bi-directional galvanic isolator (BDGI) is reported for the first time. The proposed design methodology uses time-division-duplex (TDD) protocol to merge the functionality of two passive galvanically isolated channels into one magnetically coupled communication channel between two chips, enabling up to 50% form-factor and assembly cost reduction while achieving state-of-art performance. A low-power UWB pulse polarity-modulated transceiver architecture is presented to maximize the channel's capacity to 300 Mb/s and minimize power consumption and propagation delay to 200 pj/b and 5 ns respectively. The communication channel utilizes a double-isolated transformer coupled channel consisting of two transformers connected in series using bondwires and achieves 11 kVpk (7.8 kVrms) high voltage isolation, the highest reported without adding extra steps or alternating the native CMOS fabrication process. The system is realized in a 0.25 um BCD (Bipolar-CMOS-DMOS) process with 0.8 mm 2 silicon area per channel. The system uses odd-symmetry center-tapped transformers and differential transceivers to increase noise/transient immunity.
Czech name
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Czech description
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Project
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Continuities
I - Institucionalni podpora na dlouhodoby koncepcni rozvoj vyzkumne organizace

Publication year
2018
Confidentiality
S - Úplné a pravdivé údaje o projektu nepodléhají ochraně podle zvláštních právních předpisů

Article name in the collection
2018 IEEE 30th International Symposium on Power Semiconductor Devices and ICs, ISPSD 2018
ISBN
978-1-5386-2927-7
ISSN
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e-ISSN
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Number of pages
4
Pages from-to
88-91
Publisher name
IEEE
Place of publication
Piscataway
Event location
Chicago
Event date
Apr 13, 2018
Type of event by nationality
WRD - Celosvětová akce
UT code for WoS article
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