A 650 kV/mu s Common-Mode Resilient CMOS Galvanically Isolated Communication System
The result's identifiers
Result code in IS VaVaI
<a href="https://www.isvavai.cz/riv?ss=detail&h=RIV%2F00216305%3A26220%2F22%3APU147389" target="_blank" >RIV/00216305:26220/22:PU147389 - isvavai.cz</a>
Result on the web
<a href="https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=9626774" target="_blank" >https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=9626774</a>
DOI - Digital Object Identifier
<a href="http://dx.doi.org/10.1109/TCSI.2021.3124554" target="_blank" >10.1109/TCSI.2021.3124554</a>
Alternative languages
Result language
angličtina
Original language name
A 650 kV/mu s Common-Mode Resilient CMOS Galvanically Isolated Communication System
Original language description
This work presents a galvanically isolated chip-to-chip communication system that utilizes laterally coupled resonators in combination with a new differential full-wave receiver architecture. Lateral resonant coupling increases the isolation capability and significantly minimizes the intra-chip coupling capacitance of galvanic isolators beyond the limits of vertical coupling in standard CMOS. The presented system marries the merits of a laterally resonant coupled channel with a source-gate coupled low-power, low-latency RF detector architecture that enables high common-mode and differential noise immunity. A center-tapped transformer is used as the interface between the proposed fully differential receiver and the communication channel to further enhance the common-mode transient immunity (CMTI). The proposed system is integrated in a 0.25 mu m CMOS process with four metal layers and does not alter the native process or necessitate additional fabrication steps. The design does not require exotic packaging and achieves state-of-art CMTI of 650 kV/mu s at 5 kVpk isolation, sub-20ns propagation delay, and maintains a small form-factor of 0.95 mm(2). The GI system exhibits robust performance to fabrication variations, with less than +/- 0.3% and +/- 8% sensitivity to process variation and post-assembly chip distance offset, respectively.
Czech name
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Czech description
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Classification
Type
J<sub>imp</sub> - Article in a specialist periodical, which is included in the Web of Science database
CEP classification
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OECD FORD branch
20200 - Electrical engineering, Electronic engineering, Information engineering
Result continuities
Project
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Continuities
S - Specificky vyzkum na vysokych skolach
Others
Publication year
2022
Confidentiality
S - Úplné a pravdivé údaje o projektu nepodléhají ochraně podle zvláštních právních předpisů
Data specific for result type
Name of the periodical
IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS I-REGULAR PAPERS
ISSN
1549-8328
e-ISSN
1558-0806
Volume of the periodical
69
Issue of the periodical within the volume
2
Country of publishing house
US - UNITED STATES
Number of pages
12
Pages from-to
587-598
UT code for WoS article
000732244000001
EID of the result in the Scopus database
2-s2.0-85120578260