VDIBA-Based Fractional-Order Oscillator Design

Result code in IS VaVaI
<a href="https://www.isvavai.cz/riv?ss=detail&h=RIV%2F00216305%3A26220%2F19%3APU132606" target="_blank" >RIV/00216305:26220/19:PU132606 - isvavai.cz</a>
Result on the web
<a href="https://ieeexplore.ieee.org/document/8769104" target="_blank" >https://ieeexplore.ieee.org/document/8769104</a>
DOI - Digital Object Identifier
<a href="http://dx.doi.org/10.1109/TSP.2019.8769104" target="_blank" >10.1109/TSP.2019.8769104</a>

Result language
angličtina
Original language name
VDIBA-Based Fractional-Order Oscillator Design
Original language description
This paper deals with a voltage-mode integer- and fractional-order oscillator design providing compact and simple CMOS structure. The proposed circuit consists of only one grounded/floating capacitor, one grounded/floating resistor, and one high-performance and versatile active element so-called voltage differencing inverting buffered amplifier (VDIBA), employing only six transistors. Compared with the corresponding already introduced fractional-order oscillators, it offers the benefit of low transistor count. In addition, it offers the well-known advantages of fractional-order oscillators about the capability for achieving very low and high oscillation frequencies with reasonable component values. The design parameters of the proposed oscillator can be electronically adjusted via change of order of the fractional-order capacitor and/or by means of bias current of the internal transconductance of the VDIBA. Theoretical results are verified by SPICE simulations using TSMC 0.18 μm level-7 LO EPI SCN018 CMOS process parameters with ±0.9 V supply voltages.
Czech name
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Czech description
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Project
<a href="/en/project/LTC18022" target="_blank" >LTC18022: Analogue fractional systems, their synthesis and analysis</a><br>
Continuities
P - Projekt vyzkumu a vyvoje financovany z verejnych zdroju (s odkazem do CEP)<br>S - Specificky vyzkum na vysokych skolach

Publication year
2019
Confidentiality
S - Úplné a pravdivé údaje o projektu nepodléhají ochraně podle zvláštních právních předpisů

Article name in the collection
Proceedings of the 2019 42nd International Conference on Telecommunications and Signal Processing (TSP), Budapest, Hungary
ISBN
978-1-7281-1864-2
ISSN
—
e-ISSN
—
Number of pages
4
Pages from-to
744-747
Publisher name
IEEE
Place of publication
Budapest, Hungary
Event location
Budapest, Hungary
Event date
Jul 1, 2019
Type of event by nationality
WRD - Celosvětová akce
UT code for WoS article
000493442800161

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