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Implementing CRYSTALS-Dilithium Signature Scheme on FPGAs

The result's identifiers

  • Result code in IS VaVaI

    <a href="https://www.isvavai.cz/riv?ss=detail&h=RIV%2F00216305%3A26220%2F21%3APU141195" target="_blank" >RIV/00216305:26220/21:PU141195 - isvavai.cz</a>

  • Result on the web

    <a href="https://dl.acm.org/doi/10.1145/3465481.3465756" target="_blank" >https://dl.acm.org/doi/10.1145/3465481.3465756</a>

  • DOI - Digital Object Identifier

    <a href="http://dx.doi.org/10.1145/3465481.3465756" target="_blank" >10.1145/3465481.3465756</a>

Alternative languages

  • Result language

    angličtina

  • Original language name

    Implementing CRYSTALS-Dilithium Signature Scheme on FPGAs

  • Original language description

    In July 2020, the lattice-based CRYSTALS-Dilithium digital signature scheme has been chosen as one of the three third-round finalists in the post-quantum cryptography standardization process by the National Institute of Standards and Technology (NIST). In this work, we present the first Very High Speed Integrated Circuit Hardware Description Language (VHDL) implementation of the CRYSTALS-Dilithium signature scheme for Field-Programmable Gate Arrays (FPGAs). Due to our parallelization-based design requiring only low numbers of cycles, running at high frequency and using reasonable amount of hardware resources on FPGA, our implementation is able to sign 15832 messages per second and verify 10524 signatures per second. In particular, the signing algorithm requires 68461 Look-Up Tables (LUTs), 86295 Flip-Flops (FFs), and the verification algorithm takes 61738 LUTs and 34963 FFs on Virtex 7 UltraScale+ FPGAs. In this article, experimental results for each Dilithium security level are provided and our VHDL-based implementation is compared with related High-Level Synthesis (HLS)-based implementations. Our solution is ca 114 times faster (in the signing algorithm) and requires less hardware resources.

  • Czech name

  • Czech description

Classification

  • Type

    D - Article in proceedings

  • CEP classification

  • OECD FORD branch

    20203 - Telecommunications

Result continuities

  • Project

    <a href="/en/project/VI20192022126" target="_blank" >VI20192022126: Modular Hardware Accelerator for Cryptographic Operations</a><br>

  • Continuities

    P - Projekt vyzkumu a vyvoje financovany z verejnych zdroju (s odkazem do CEP)

Others

  • Publication year

    2021

  • Confidentiality

    S - Úplné a pravdivé údaje o projektu nepodléhají ochraně podle zvláštních právních předpisů

Data specific for result type

  • Article name in the collection

    ARES 2021: The 16th International Conference on Availability, Reliability and Security

  • ISBN

    978-1-4503-9051-4

  • ISSN

  • e-ISSN

  • Number of pages

    10

  • Pages from-to

    1-10

  • Publisher name

    Neuveden

  • Place of publication

    neuveden

  • Event location

    All-digital Conference

  • Event date

    Aug 17, 2021

  • Type of event by nationality

    WRD - Celosvětová akce

  • UT code for WoS article

    000749539200015