Instruction mapping techniques for processors with very long instruction word architectures

Result code in IS VaVaI
<a href="https://www.isvavai.cz/riv?ss=detail&h=RIV%2F00216305%3A26220%2F22%3APU146658" target="_blank" >RIV/00216305:26220/22:PU146658 - isvavai.cz</a>
Result on the web
<a href="http://iris.elf.stuba.sk/JEEEC/data/pdf/6_122-03.pdf" target="_blank" >http://iris.elf.stuba.sk/JEEEC/data/pdf/6_122-03.pdf</a>
DOI - Digital Object Identifier
<a href="http://dx.doi.org/10.2478/jee-2022-0053" target="_blank" >10.2478/jee-2022-0053</a>

Result language
angličtina
Original language name
Instruction mapping techniques for processors with very long instruction word architectures
Original language description
This paper presents an instruction mapping technique for generating a low-level assembly code for digital signal processing algorithms. This technique helps developers to implement retargetable kernel functions with the performance benefits of the low-level assembly languages. The approach is aimed at exceptionally long instruction word (VLIW) architectures, which benefits the most from the proposed method. Mapped algorithms are described by the signal-flow graphs, which are used to find possible parallel operations. The algorithm is converted into low-level code and mapped to the target architecture. This process also introduces the optimization of instruction mapping priority, which leads to the more effective code. The technique was verified on selected kernels, compared to the common programming methods, and proved that it is suitable for VLIW architectures and for portability to other systems.
Czech name
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Czech description
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Type
J<sub>imp</sub> - Article in a specialist periodical, which is included in the Web of Science database
CEP classification
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OECD FORD branch
20206 - Computer hardware and architecture

Publication year
2022
Confidentiality
S - Úplné a pravdivé údaje o projektu nepodléhají ochraně podle zvláštních právních předpisů

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