All

What are you looking for?

All
Projects
Results
Organizations

Quick search

  • Projects supported by TA ČR
  • Excellent projects
  • Projects with the highest public support
  • Current projects

Smart search

  • That is how I find a specific +word
  • That is how I leave the -word out of the results
  • “That is how I can find the whole phrase”

Cartesian Genetic Programming with a Modified Selection Operator for Combinational Circuit Design: Arithmetic Multipliers and Adders

The result's identifiers

  • Result code in IS VaVaI

    <a href="https://www.isvavai.cz/riv?ss=detail&h=RIV%2F00216305%3A26220%2F26%3A0201220" target="_blank" >RIV/00216305:26220/26:0201220 - isvavai.cz</a>

  • Result on the web

    <a href="http://dx.doi.org/10.1007/978-3-031-84356-3_5" target="_blank" >http://dx.doi.org/10.1007/978-3-031-84356-3_5</a>

  • DOI - Digital Object Identifier

    <a href="http://dx.doi.org/10.1007/978-3-031-84356-3_5" target="_blank" >10.1007/978-3-031-84356-3_5</a>

Alternative languages

  • Result language

    angličtina

  • Original language name

    Cartesian Genetic Programming with a Modified Selection Operator for Combinational Circuit Design: Arithmetic Multipliers and Adders

  • Original language description

    The evolutionary design of combinational logic circuits offers an innovative approach that often surpasses traditional methods, such as the Quine-McCluskey algorithm, in both efficiency and effectiveness. Cartesian Genetic Programming (CGP) emerges as a potent technique in this domain, enabling versatile circuit designs tailored to diverse requirements such as cost, gate count, and circuit speed. In this paper, we introduce an advanced modification of CGP, termed CGP-SA, which integrates the Simulated Annealing mechanism into the selection operator. This novel approach enhances the algorithm's ability to escape local optima, thereby fostering the discovery of more optimal solutions. We demonstrate the efficacy of CGP-SA through the design of three types of multipliers and two types of adders, utilizing diverse logic gate sets. This exploration not only reveals the flexibility of CGP-SA in handling various circuit design challenges but also highlights its adaptability to different optimization criteria.

  • Czech name

  • Czech description

Classification

  • Type

    D - Article in proceedings

  • CEP classification

  • OECD FORD branch

    20205 - Automation and control systems

Result continuities

  • Project

    <a href="/en/project/GA24-12474S" target="_blank" >GA24-12474S: Benchmarking derivative-free global optimization methods</a><br>

  • Continuities

    P - Projekt vyzkumu a vyvoje financovany z verejnych zdroju (s odkazem do CEP)

Others

  • Publication year

    2025

  • Confidentiality

    S - Úplné a pravdivé údaje o projektu nepodléhají ochraně podle zvláštních právních předpisů

Data specific for result type

  • Article name in the collection

    Lecture Notes in Artificial Intelligence

  • ISBN

    978-3-031-84355-6

  • ISSN

  • e-ISSN

    1611-3349

  • Number of pages

    13

  • Pages from-to

    53-65

  • Publisher name

    Springer Nature

  • Place of publication

    CHAM

  • Event location

    Zakopane, Poland

  • Event date

    Jun 16, 2024

  • Type of event by nationality

    WRD - Celosvětová akce

  • UT code for WoS article

    001535049000005