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VHDL Circuit Description Transparency Analysis

The result's identifiers

  • Result code in IS VaVaI

    <a href="https://www.isvavai.cz/riv?ss=detail&h=RIV%2F00216305%3A26230%2F02%3APU36271" target="_blank" >RIV/00216305:26230/02:PU36271 - isvavai.cz</a>

  • Result on the web

  • DOI - Digital Object Identifier

Alternative languages

  • Result language

    angličtina

  • Original language name

    VHDL Circuit Description Transparency Analysis

  • Original language description

    The paper deals with analysis of transparency properties of circuit elements. Analysis of transparency is an important part of testability analysis of digital circuit using i path concept. I paths in the structure of the digital circuit consist of connections and elements. Such elements must have a mode of operation in which data can be transferred through them without change. When the structure of the digital circuit described in VHDL (at RT level) is under analysis, transparency properties of all elemments must be identified. While the structure of the circuit is known, elements are described by its behavior only. Methods of transparency analysis of elements described behaviorally in VHDL are depicted in the paper.

  • Czech name

  • Czech description

Classification

  • Type

    D - Article in proceedings

  • CEP classification

    JC - Computer hardware and software

  • OECD FORD branch

Result continuities

  • Project

    <a href="/en/project/GA102%2F01%2F1531" target="_blank" >GA102/01/1531: Formal approaches in digital circuit diagnostics - testable design verification</a><br>

  • Continuities

    P - Projekt vyzkumu a vyvoje financovany z verejnych zdroju (s odkazem do CEP)

Others

  • Publication year

    2002

  • Confidentiality

    S - Úplné a pravdivé údaje o projektu nepodléhají ochraně podle zvláštních právních předpisů

Data specific for result type

  • Article name in the collection

    Proceedings of the Fifth International Scientific Conference Electronic Computers and Informatics 2002

  • ISBN

    80-7099-879-2

  • ISSN

  • e-ISSN

  • Number of pages

    6

  • Pages from-to

    194-199

  • Publisher name

    Faculty of Electrical Engineering and Informatics, University of Technology Košice

  • Place of publication

    Košice

  • Event location

    Kosice-Herlany

  • Event date

    Oct 10, 2002

  • Type of event by nationality

    EUR - Evropská akce

  • UT code for WoS article