Nested Loops Degree Impact on RTL Digital Circuit Testability

Result code in IS VaVaI

<a href="https://www.isvavai.cz/riv?ss=detail&h=RIV%2F00216305%3A26230%2F03%3APU42507" target="_blank" >RIV/00216305:26230/03:PU42507 - isvavai.cz</a>

Result on the web

—

DOI - Digital Object Identifier

—

Result language

angličtina

Original language name

Nested Loops Degree Impact on RTL Digital Circuit Testability

Original language description

The existence of loops in a circuit structure causes problems in both test generation and application. Thus, the problem of identifying loops becomes an important task during testability analysis or, later, e.g., during allocation-for testability process. When nested loops occur in the circuit, it is necessary to accurately determine the most nested one to improve circuit testability significantly, with minimal design cost. This paper deals with the problem of identifying nested loops including their neesting degree in the register-transfer level (RTL) digital circuit structure as well as with the impact of such loops on the circuit testability.

Czech name

—

Czech description

—

Type

D - Article in proceedings

CEP classification

JC - Computer hardware and software

OECD FORD branch

—

Project

<a href="/en/project/GA102%2F01%2F1531" target="_blank" >GA102/01/1531: Formal approaches in digital circuit diagnostics - testable design verification</a><br>

Continuities

P - Projekt vyzkumu a vyvoje financovany z verejnych zdroju (s odkazem do CEP)

Publication year

2003

Confidentiality

S - Úplné a pravdivé údaje o projektu nepodléhají ochraně podle zvláštních právních předpisů

Article name in the collection

Programmable Devices and Systems

ISBN

0-08-044130-0

ISSN

—

e-ISSN

—

Number of pages

6

Pages from-to

202-207

Publisher name

Elsevier Science

Place of publication

Oxford

Event location

Ostrava

Event date

Feb 11, 2003

Type of event by nationality

WRD - Celosvětová akce

UT code for WoS article

—