Testable Design Verification Using Petri Nets

Result code in IS VaVaI
<a href="https://www.isvavai.cz/riv?ss=detail&h=RIV%2F00216305%3A26230%2F03%3APU42591" target="_blank" >RIV/00216305:26230/03:PU42591 - isvavai.cz</a>
Result on the web
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DOI - Digital Object Identifier
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Result language
angličtina
Original language name
Testable Design Verification Using Petri Nets
Original language description
In the paper, a method for formal verification of testable design is presented. As a input, a digital circuit structure at RT level designed using any DfT technique is assumed. Proposed method enables to verify testability of each element or a part of the circuit. Petri Net based model and common methods of Petri Net analysis are utilised. On the model, it is possible to prove, if a circuit element or a part of the circuit under test can be tested by a selected way - if paths, chosen for diagnostic dataa transport, are passable or not and if not, for what reason.
Czech name
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Czech description
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Project
Result was created during the realization of more than one project. More information in the Projects tab.
Continuities
P - Projekt vyzkumu a vyvoje financovany z verejnych zdroju (s odkazem do CEP)

Publication year
2003
Confidentiality
S - Úplné a pravdivé údaje o projektu nepodléhají ochraně podle zvláštních právních předpisů

Article name in the collection
Proceedings of Euromicro Symposium on Digital System Design 2003
ISBN
0-7695-2003-0
ISSN
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e-ISSN
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Number of pages
8
Pages from-to
304-311
Publisher name
IEEE Computer Society Press
Place of publication
Los Alamitos, CA
Event location
Belek
Event date
Sep 2, 2003
Type of event by nationality
WRD - Celosvětová akce
UT code for WoS article
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