Digital Systems Architectures Based on On-line Checkers
The result's identifiers
Result code in IS VaVaI
<a href="https://www.isvavai.cz/riv?ss=detail&h=RIV%2F00216305%3A26230%2F08%3APU76713" target="_blank" >RIV/00216305:26230/08:PU76713 - isvavai.cz</a>
Result on the web
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DOI - Digital Object Identifier
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Alternative languages
Result language
angličtina
Original language name
Digital Systems Architectures Based on On-line Checkers
Original language description
In this paper, we present a methodology for generating<br>VHDL descriptions of hardware checkers is presented. It is<br>shown how the methodology can be used to generate on-line<br>checkers of communication protocols, counters, decoders,<br>registers, comparators, etc. It is also demonstrated how a<br>checker for more complex structures can be developed. We<br>describe the possibilities of utilizing this approach in the design<br>of Fault Tolerant Systems (FTS). Experimental results<br>in terms of FPGAresources needed to synthesize different<br>types of checkers are presented.
Czech name
Číslicové systémy založené na on-line hlídacích obvodech
Czech description
In this paper, we present a methodology for generating<br>VHDL descriptions of hardware checkers is presented. It is<br>shown how the methodology can be used to generate on-line<br>checkers of communication protocols, counters, decoders,<br>registers, comparators, etc. It is also demonstrated how a<br>checker for more complex structures can be developed. We<br>describe the possibilities of utilizing this approach in the design<br>of Fault Tolerant Systems (FTS). Experimental results<br>in terms of FPGAresources needed to synthesize different<br>types of checkers are presented.
Classification
Type
D - Article in proceedings
CEP classification
JC - Computer hardware and software
OECD FORD branch
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Result continuities
Project
<a href="/en/project/GD102%2F05%2FH050" target="_blank" >GD102/05/H050: Integrated Approach to Education of PhD Students in the Area of Parallel and Distributed Systems</a><br>
Continuities
Z - Vyzkumny zamer (s odkazem do CEZ)
Others
Publication year
2008
Confidentiality
S - Úplné a pravdivé údaje o projektu nepodléhají ochraně podle zvláštních právních předpisů
Data specific for result type
Article name in the collection
11th EUROMICRO Conference on Digital System Design DSD 2008
ISBN
978-0-7695-3277-6
ISSN
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e-ISSN
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Number of pages
8
Pages from-to
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Publisher name
IEEE Computer Society
Place of publication
Parma
Event location
Parma
Event date
Sep 3, 2008
Type of event by nationality
WRD - Celosvětová akce
UT code for WoS article
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