Reliability Models for Fault Tolerant Architectures Based on FPGA

Result code in IS VaVaI

RIV/00216305:26230/09:PU82705 - isvavai.cz

Result on the web

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DOI - Digital Object Identifier

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Result language

angličtina

Original language name

Reliability Models for Fault Tolerant Architectures Based on FPGA

Original language description

In this presentation, a methodology of FTS design based on FPGA is
presented. The FT architectures are based both on duplex and TMR
systems to which fault detection capabilities are added, the use
of on-line checkers for this purpose is demonstrated. It is
described how reliability and availability parameters in TMR and
duplex structures with checkers can be increased. To demonstrate
this, analytical calculations based on Markov reliability model
are used. It is also shown how the availability parameters can be
affected by the operating environment into which the FTS is
implemented. Finally, the results of research and the comparison
of our approach with classical TMR and duplex architectures for
different failure ratesare presented.

Czech name

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Czech description

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Type

D - Article in proceedings

CEP classification

JC - Computer hardware and software

OECD FORD branch

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Project

GD102/09/H042: Mathematical and Engineering Approaches to Developing Reliable and Secure Concurrent and Distributed Computer Systems

Continuities

Z - Vyzkumny zamer (s odkazem do CEZ)

Publication year

2009

Confidentiality

S - Úplné a pravdivé údaje o projektu nepodléhají ochraně podle zvláštních právních předpisů

Article name in the collection

5th Doctoral Workshop on Mathematical and Engineering Methods in Computer Science

ISBN

978-80-87342-04-6

ISSN

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e-ISSN

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Number of pages

1

Pages from-to

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Publisher name

Faculty of Informatics MU

Place of publication

Brno

Event location

Znojmo

Event date

Nov 13, 2009

Type of event by nationality

WRD - Celosvětová akce

UT code for WoS article

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