High Availability Fault Tolerant Architectures Implemented into FPGAs

Result code in IS VaVaI
<a href="https://www.isvavai.cz/riv?ss=detail&h=RIV%2F00216305%3A26230%2F09%3APU82605" target="_blank" >RIV/00216305:26230/09:PU82605 - isvavai.cz</a>
Result on the web
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DOI - Digital Object Identifier
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Result language
angličtina
Original language name
High Availability Fault Tolerant Architectures Implemented into FPGAs
Original language description
In the paper, the methodology of fault tolerant systems design based on FPGA are presented. The architectures are based both on duplex and TMR systems to which fault detection capabilities are added, the use of on-line checkers for this purpose is demonstrated. It is described how reliability and availability parameters in TMR and duplex structures with checkers can be increased. To demonstrate this, analytical calculations based on Markov reliability model are used. It is also shown how the availability parameters can be affected by the operating environment into which the fault tolerant system is implemented. The principles of generating sequence of FT architectures with different level of diagnostic are presented.
Czech name
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Czech description
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Project
Result was created during the realization of more than one project. More information in the Projects tab.
Continuities
Z - Vyzkumny zamer (s odkazem do CEZ)

Publication year
2009
Confidentiality
S - Úplné a pravdivé údaje o projektu nepodléhají ochraně podle zvláštních právních předpisů

Article name in the collection
12th EUROMICRO Conference on Digital System Design DSD 2009
ISBN
978-0-7695-3782-5
ISSN
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e-ISSN
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Number of pages
8
Pages from-to
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Publisher name
IEEE Computer Society
Place of publication
Patras
Event location
Patras
Event date
Aug 27, 2009
Type of event by nationality
WRD - Celosvětová akce
UT code for WoS article
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