Fast and scalable packet classification using perfect hash functions

Result code in IS VaVaI
<a href="https://www.isvavai.cz/riv?ss=detail&h=RIV%2F00216305%3A26230%2F09%3APU82617" target="_blank" >RIV/00216305:26230/09:PU82617 - isvavai.cz</a>
Alternative codes found
RIV/63839172:_____/09:00006567
Result on the web
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DOI - Digital Object Identifier
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Result language
angličtina
Original language name
Fast and scalable packet classification using perfect hash functions
Original language description
Packet classification is an important operation for applications such as routers, firewalls or intrusion detection systems. Many algorithms and hardware architectures for packet classification have been created, but none of them can compete with the speed of TCAMs in the worst case. We propose new hardware-based algorithm for packet classification. The solution is based on problem decomposition and is aimed at the highest network speeds. A unique property of the algorithm is the constant time complexityin terms of external memory accesses. The algorithm performs exactly two external memory accesses to classify a packet. Using FPGA and one commodity SRAM chip, a throughput of 150 million packets per second can be achieved. This makes throughput of 100Gbps for the shortest packets. Further performance scaling is possible with more or faster SRAM chips.
Czech name
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Czech description
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Publication year
2009
Confidentiality
S - Úplné a pravdivé údaje o projektu nepodléhají ochraně podle zvláštních právních předpisů

Article name in the collection
Proceeding of the ACM/SIGDA international symposium on Field programmable gate arrays
ISBN
978-1-60558-410-2
ISSN
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e-ISSN
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Number of pages
8
Pages from-to
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Publisher name
Association for Computing Machinery
Place of publication
New York
Event location
Monterey, Californi
Event date
Jan 20, 2009
Type of event by nationality
WRD - Celosvětová akce
UT code for WoS article
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