Generating Proper VLIW Assembler Code Using Scattered Context Grammars

Result code in IS VaVaI
<a href="https://www.isvavai.cz/riv?ss=detail&h=RIV%2F00216305%3A26230%2F10%3APU89533" target="_blank" >RIV/00216305:26230/10:PU89533 - isvavai.cz</a>
Result on the web
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DOI - Digital Object Identifier
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Result language
angličtina
Original language name
Generating Proper VLIW Assembler Code Using Scattered Context Grammars
Original language description
The very long instruction word (VLIW) processor architecture is focused on~a~high instruction level parallelism. Program execution is scheduled statically at~compilation time. Therefore, there is no need for run-time scheduling and dependency checking mechanisms. On the other hand, all these constraints must be controlled by the compiler. This paper describes usage of scattered context grammars in order to model instruction level limitations of these processors. Resulting grammar generates proper assembler code. This concept has two advantages -- formal description of the dependency checking process and high reduction of production rules over other methods.
Czech name
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Czech description
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Project
Result was created during the realization of more than one project. More information in the Projects tab.
Continuities
Z - Vyzkumny zamer (s odkazem do CEZ)<br>S - Specificky vyzkum na vysokych skolach

Publication year
2010
Confidentiality
S - Úplné a pravdivé údaje o projektu nepodléhají ochraně podle zvláštních právních předpisů

Article name in the collection
Proceedings of the 16th Conference Student EEICT 2010 Volume 5
ISBN
978-80-214-4080-7
ISSN
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e-ISSN
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Number of pages
5
Pages from-to
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Publisher name
Faculty of Information Technology BUT
Place of publication
Brno
Event location
FEKT VUT v Brně
Event date
Apr 29, 2010
Type of event by nationality
CST - Celostátní akce
UT code for WoS article
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