Exploitation of Scattered Context Grammars to Model VLIW Instruction Constraints

Result code in IS VaVaI
<a href="https://www.isvavai.cz/riv?ss=detail&h=RIV%2F00216305%3A26230%2F10%3APU89544" target="_blank" >RIV/00216305:26230/10:PU89544 - isvavai.cz</a>
Result on the web
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DOI - Digital Object Identifier
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Result language
angličtina
Original language name
Exploitation of Scattered Context Grammars to Model VLIW Instruction Constraints
Original language description
More and more nowadays data processing System-on-Chip (SoC) devices exploit the very long instruction word (VLIW) technology. The high performance of VLIW processors is achieved by a high instruction level parallelism. Program execution is scheduled statically at compilation time. Therefore, there is no need for run-time control mechanisms and hardware can be relatively simple. On the other hand, all constraints checks must be done by the compiler.<br><br>This paper describes formal method for modelinginstruction level limitations of these processors. This method is based on scattered context grammars that generate proper assembler code. This concept has two advantages - formal description of the dependency checking process and high reduction of description complexity over other methods.<br>
Czech name
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Czech description
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Project
Result was created during the realization of more than one project. More information in the Projects tab.
Continuities
Z - Vyzkumny zamer (s odkazem do CEZ)<br>S - Specificky vyzkum na vysokych skolach

Publication year
2010
Confidentiality
S - Úplné a pravdivé údaje o projektu nepodléhají ochraně podle zvláštních právních předpisů

Article name in the collection
Proceedings of the 12th Biennial Baltic Electronics Conference
ISBN
978-1-4244-7357-1
ISSN
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e-ISSN
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Number of pages
4
Pages from-to
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Publisher name
Talinn Technical University
Place of publication
Tallinn
Event location
Tallinn
Event date
Oct 4, 2010
Type of event by nationality
WRD - Celosvětová akce
UT code for WoS article
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