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Hardware Accelerated Functional Verification

The result's identifiers

  • Result code in IS VaVaI

    <a href="https://www.isvavai.cz/riv?ss=detail&h=RIV%2F00216305%3A26230%2F11%3APU96120" target="_blank" >RIV/00216305:26230/11:PU96120 - isvavai.cz</a>

  • Result on the web

  • DOI - Digital Object Identifier

Alternative languages

  • Result language

    angličtina

  • Original language name

    Hardware Accelerated Functional Verification

  • Original language description

    Functional verification is a widespread technique for checking whether a hardware system satisfies a given correctness specification. The complexity of modern computer systems is rapidly rising and the verification process takes significant amount of time. It is a challenging process to find appropriate acceleration techniques. We introduce a strategy for acceleration of functional verification using FPGAs by targeting special components of the verification environment to the FPGA.

  • Czech name

  • Czech description

Classification

  • Type

    D - Article in proceedings

  • CEP classification

    JC - Computer hardware and software

  • OECD FORD branch

Result continuities

  • Project

  • Continuities

    Z - Vyzkumny zamer (s odkazem do CEZ)<br>S - Specificky vyzkum na vysokych skolach

Others

  • Publication year

    2011

  • Confidentiality

    S - Úplné a pravdivé údaje o projektu nepodléhají ochraně podle zvláštních právních předpisů

Data specific for result type

  • Article name in the collection

    Proceedings of the 17th Conference STUDENT EEICT 2011

  • ISBN

    978-80-214-4272-6

  • ISSN

  • e-ISSN

  • Number of pages

    3

  • Pages from-to

    321-323

  • Publisher name

    Faculty of Information Technology BUT

  • Place of publication

    Brno

  • Event location

    Brno

  • Event date

    Apr 28, 2011

  • Type of event by nationality

    CST - Celostátní akce

  • UT code for WoS article