Hardware Accelerated Functional Verification - Framework for FPGA-Accelerated Functional Verification

Result code in IS VaVaI
<a href="https://www.isvavai.cz/riv?ss=detail&h=RIV%2F00216305%3A26230%2F11%3APU96210" target="_blank" >RIV/00216305:26230/11:PU96210 - isvavai.cz</a>
Result on the web
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DOI - Digital Object Identifier
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Result language
angličtina
Original language name
Hardware Accelerated Functional Verification - Framework for FPGA-Accelerated Functional Verification
Original language description
Functional verification is a widespread technique to check whether a hardware system satisfies a given correctness specification. As the complexity of modern hardware systems rises rapidly, it is a challenging task to find appropriate techniques for acceleration of this process. This thesis introduces a design of a verification framework that exploits the field-programmable gate array (FPGA) technology for cycle-accurate acceleration of simulation-based verification, while retaining the possibility to run verification also in the user-friendly debugging environment of a simulator. The presented framework is written in SystemVerilog and complies with the principles of functional verification methodologies (OVM, UVM) as well as assertion-based verification, making its application range quite large. According to the experiments carried out on a prototype implementation, the achieved acceleration is proportional to the number of checked transactions and the complexity of the verified syste
Czech name
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Czech description
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Project
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Continuities
Z - Vyzkumny zamer (s odkazem do CEZ)<br>S - Specificky vyzkum na vysokych skolach

Publication year
2011
Confidentiality
S - Úplné a pravdivé údaje o projektu nepodléhají ochraně podle zvláštních právních předpisů

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