Acceleration of Functional Verification in the Development Cycle of Hardware Systems

Result code in IS VaVaI

<a href="https://www.isvavai.cz/riv?ss=detail&h=RIV%2F00216305%3A26230%2F12%3APU101864" target="_blank" >RIV/00216305:26230/12:PU101864 - isvavai.cz</a>

Result on the web

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DOI - Digital Object Identifier

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Result language

angličtina

Original language name

Acceleration of Functional Verification in the Development Cycle of Hardware Systems

Original language description

Functional verification is a widespread technique for checking whether a hardware system satisfies a given correctness specification. The complexity of modern computer systems is rapidly rising and the verification process takes significant amount of time. It is a challenging process to find appropriate acceleration techniques. I introduce a strategy for acceleration of functional verification using FPGAs by targeting special components of the verification environment to the FPGA.The second approach utilizes genetic algorithm in order to optimize and automate a technique called coverage-driven verification.

Czech name

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Czech description

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Type

D - Article in proceedings

CEP classification

JC - Computer hardware and software

OECD FORD branch

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Project

Result was created during the realization of more than one project. More information in the Projects tab.

Continuities

P - Projekt vyzkumu a vyvoje financovany z verejnych zdroju (s odkazem do CEP)<br>S - Specificky vyzkum na vysokych skolach

Publication year

2012

Confidentiality

S - Úplné a pravdivé údaje o projektu nepodléhají ochraně podle zvláštních právních předpisů

Article name in the collection

Počítačové architektury a diagnostika

ISBN

978-80-01-05106-1

ISSN

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e-ISSN

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Number of pages

6

Pages from-to

73-78

Publisher name

Czech Technical University

Place of publication

Praha

Event location

Milovy

Event date

Sep 10, 2012

Type of event by nationality

CST - Celostátní akce

UT code for WoS article

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