Software Fault Tolerance: the Evaluation by Functional Verification
The result's identifiers
Result code in IS VaVaI
<a href="https://www.isvavai.cz/riv?ss=detail&h=RIV%2F00216305%3A26230%2F15%3APU117053" target="_blank" >RIV/00216305:26230/15:PU117053 - isvavai.cz</a>
Result on the web
<a href="https://ieeexplore.ieee.org/document/7302285" target="_blank" >https://ieeexplore.ieee.org/document/7302285</a>
DOI - Digital Object Identifier
<a href="http://dx.doi.org/10.1109/DSD.2015.107" target="_blank" >10.1109/DSD.2015.107</a>
Alternative languages
Result language
angličtina
Original language name
Software Fault Tolerance: the Evaluation by Functional Verification
Original language description
The aim of this paper is to present a new approach in evaluating Software Fault Tolerance (SFT) methodologies. It is the way on how to ensure fault tolerance without any additional hardware as is common in frequently used Triple Modular Redundancy (TMR). As our research is focused on electromechanical systems which are commonly driven by processors or Multi Processors Systems on Chip (MPSoC) we decided to use the soft-core processor running on Field Programmable Gate Array (FPGA) as our experimental platform. The new approach uses Functional Verification for automation of the evaluation process. The functional verification environment is one of the important parts of the presented evaluation platform architecture. Programs generation for a processor, where SFT is applied, is also important. Experiments with the programs generator and fault injection are presented and goals for future work are identified on that basis.
Czech name
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Czech description
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Classification
Type
D - Article in proceedings
CEP classification
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OECD FORD branch
10201 - Computer sciences, information science, bioinformathics (hardware development to be 2.2, social aspect to be 5.8)
Result continuities
Project
Result was created during the realization of more than one project. More information in the Projects tab.
Continuities
P - Projekt vyzkumu a vyvoje financovany z verejnych zdroju (s odkazem do CEP)<br>S - Specificky vyzkum na vysokych skolach
Others
Publication year
2015
Confidentiality
S - Úplné a pravdivé údaje o projektu nepodléhají ochraně podle zvláštních právních předpisů
Data specific for result type
Article name in the collection
Proceedings of the 18th Euromicro Conference on Digital Systems Design
ISBN
978-1-4673-8035-5
ISSN
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e-ISSN
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Number of pages
4
Pages from-to
284-287
Publisher name
IEEE Computer Society
Place of publication
Funchal
Event location
Funchal
Event date
Aug 26, 2015
Type of event by nationality
WRD - Celosvětová akce
UT code for WoS article
000382382300042