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Redundant Data Types and Operations in HLS and their Use for a Robot Controller Unit Fault Tolerance Evaluation

The result's identifiers

  • Result code in IS VaVaI

    <a href="https://www.isvavai.cz/riv?ss=detail&h=RIV%2F00216305%3A26230%2F17%3APU126442" target="_blank" >RIV/00216305:26230/17:PU126442 - isvavai.cz</a>

  • Result on the web

    <a href="https://www.fit.vut.cz/research/publication/11493/" target="_blank" >https://www.fit.vut.cz/research/publication/11493/</a>

  • DOI - Digital Object Identifier

    <a href="http://dx.doi.org/10.1109/EWDTS.2017.8110127" target="_blank" >10.1109/EWDTS.2017.8110127</a>

Alternative languages

  • Result language

    angličtina

  • Original language name

    Redundant Data Types and Operations in HLS and their Use for a Robot Controller Unit Fault Tolerance Evaluation

  • Original language description

    Some environments (e.g. space, aerospace or medical systems) require electronic systems to withstand an increased occurrence of faults. Moreover, the failure of these electronic systems can cause high economical losses or endanger human health. Fault tolerance is one of the techniques, the goal of which is to avoid such situations. This paper presents an approach to evaluate the degree of importance of individual system partitions when High-Level Synthesis (HLS) methodology is used. The importance of individual partitions was evaluated by the usage of our approach to fault-tolerant data-paths design which is based on the HLS input specification modification. The partitions are formed by sets of variables and operations. A brief description of the approach to fault tolerance in HLS is shown in the paper as well. Our experiments are evaluated using an SRAM-based FPGA evaluation platform which allows us to analyze fault tolerance properties of the Design Under Test (DUT). In the evaluation platform, functional verification in combination with fault injection is utilized.

  • Czech name

  • Czech description

Classification

  • Type

    D - Article in proceedings

  • CEP classification

  • OECD FORD branch

    20206 - Computer hardware and architecture

Result continuities

  • Project

    <a href="/en/project/LQ1602" target="_blank" >LQ1602: IT4Innovations excellence in science</a><br>

  • Continuities

    P - Projekt vyzkumu a vyvoje financovany z verejnych zdroju (s odkazem do CEP)<br>S - Specificky vyzkum na vysokych skolach

Others

  • Publication year

    2017

  • Confidentiality

    S - Úplné a pravdivé údaje o projektu nepodléhají ochraně podle zvláštních právních předpisů

Data specific for result type

  • Article name in the collection

    Proceedings of IEEE East-West Design & Test Symposium

  • ISBN

    978-1-5386-3299-4

  • ISSN

  • e-ISSN

  • Number of pages

    6

  • Pages from-to

    359-364

  • Publisher name

    IEEE Computer Society

  • Place of publication

    Novi Sad

  • Event location

    Dr Zorana Đinđića 1, 21101, Novi Sad

  • Event date

    Sep 29, 2017

  • Type of event by nationality

    WRD - Celosvětová akce

  • UT code for WoS article

    000426878200100