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Data Types and Operations Modifications: a Practical Approach to Fault Tolerance in HLS

The result's identifiers

  • Result code in IS VaVaI

    <a href="https://www.isvavai.cz/riv?ss=detail&h=RIV%2F00216305%3A26230%2F17%3APU126441" target="_blank" >RIV/00216305:26230/17:PU126441 - isvavai.cz</a>

  • Result on the web

    <a href="https://www.fit.vut.cz/research/publication/11492/" target="_blank" >https://www.fit.vut.cz/research/publication/11492/</a>

  • DOI - Digital Object Identifier

    <a href="http://dx.doi.org/10.1109/EWDTS.2017.8110113" target="_blank" >10.1109/EWDTS.2017.8110113</a>

Alternative languages

  • Result language

    angličtina

  • Original language name

    Data Types and Operations Modifications: a Practical Approach to Fault Tolerance in HLS

  • Original language description

    Some types of electronic systems are working in the environment with an increased occurrence of faults such as space, aerospace or medical systems. Faults in these systems can lead to the failure of the whole system and can cause high economical losses or endanger human health. Fault tolerance is one of the techniques, the goal of which is to avoid such situations. This paper presents an approach to fault-tolerant data-paths design that is based on the modification of High-level Synthesis (HLS) input specification. The description and evaluation of the impacts of some HLS optimization methods are demonstrated in the paper as well. Higher reliability is achieved through the modification of input description in the C++ programming language, which the HLS synthesis tools are based on. Our work targets SRAM-based FPGAs that are prone to Single Event Upsets (SEUs). For the evaluation of the proposed method we use our evaluation platform, which allows us to analyze fault tolerance properties of the Design Under Test (DUT). The evaluation platform is based on functional verification in combination with fault injection.

  • Czech name

  • Czech description

Classification

  • Type

    D - Article in proceedings

  • CEP classification

  • OECD FORD branch

    20206 - Computer hardware and architecture

Result continuities

  • Project

    <a href="/en/project/LQ1602" target="_blank" >LQ1602: IT4Innovations excellence in science</a><br>

  • Continuities

    P - Projekt vyzkumu a vyvoje financovany z verejnych zdroju (s odkazem do CEP)<br>S - Specificky vyzkum na vysokych skolach

Others

  • Publication year

    2017

  • Confidentiality

    S - Úplné a pravdivé údaje o projektu nepodléhají ochraně podle zvláštních právních předpisů

Data specific for result type

  • Article name in the collection

    Proceedings of IEEE East-West Design & Test Symposium

  • ISBN

    978-1-5386-3299-4

  • ISSN

  • e-ISSN

  • Number of pages

    6

  • Pages from-to

    273-278

  • Publisher name

    IEEE Computer Society

  • Place of publication

    Novi Sad

  • Event location

    Dr Zorana Đinđića 1, 21101, Novi Sad

  • Event date

    Sep 29, 2017

  • Type of event by nationality

    WRD - Celosvětová akce

  • UT code for WoS article

    000426878200086