HLS-based Fault Tolerance Approach for SRAM-based FPGAs
The result's identifiers
Result code in IS VaVaI
<a href="https://www.isvavai.cz/riv?ss=detail&h=RIV%2F00216305%3A26230%2F16%3APU121676" target="_blank" >RIV/00216305:26230/16:PU121676 - isvavai.cz</a>
Result on the web
<a href="http://www.fit.vutbr.cz/research/pubs/all.php?id=11275" target="_blank" >http://www.fit.vutbr.cz/research/pubs/all.php?id=11275</a>
DOI - Digital Object Identifier
<a href="http://dx.doi.org/10.1109/FPT.2016.7929561" target="_blank" >10.1109/FPT.2016.7929561</a>
Alternative languages
Result language
angličtina
Original language name
HLS-based Fault Tolerance Approach for SRAM-based FPGAs
Original language description
This paper presents an approach to fault-tolerant systems design and synthesis based on High-level Synthesis (HLS). A description and evaluation of the impacts of HLS optimization methods are shown as well. The higher reliability is achieved through modification of input description in the C++ programming language on which the HLS synthesis tools are based on. Our work targets SRAM-based FPGAs, which are prone to Single Event Upsets (SEUs). For the evaluation of impacts of HLS optimization methods we use our evaluation platform, which allows us to test fault tolerance properties of the Design Under Test (DUT). The evaluation platform is based on functional verification combined with fault injection.
Czech name
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Czech description
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Classification
Type
D - Article in proceedings
CEP classification
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OECD FORD branch
20206 - Computer hardware and architecture
Result continuities
Project
Result was created during the realization of more than one project. More information in the Projects tab.
Continuities
P - Projekt vyzkumu a vyvoje financovany z verejnych zdroju (s odkazem do CEP)<br>S - Specificky vyzkum na vysokych skolach
Others
Publication year
2016
Confidentiality
S - Úplné a pravdivé údaje o projektu nepodléhají ochraně podle zvláštních právních předpisů
Data specific for result type
Article name in the collection
Proceedings of the 2016 International Conference on Field Programmable Technology
ISBN
978-1-5090-5602-6
ISSN
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e-ISSN
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Number of pages
2
Pages from-to
301-302
Publisher name
IEEE Computer Society
Place of publication
Xi'an
Event location
Xi'an
Event date
Dec 7, 2016
Type of event by nationality
WRD - Celosvětová akce
UT code for WoS article
000402988900057