Error Mitigation using Approximate Logic Circuits: A Comparison of Probabilistic and Evolutionary Approaches

Result code in IS VaVaI

<a href="https://www.isvavai.cz/riv?ss=detail&h=RIV%2F00216305%3A26230%2F16%3APU121576" target="_blank" >RIV/00216305:26230/16:PU121576 - isvavai.cz</a>

Result on the web

<a href="http://dx.doi.org/10.1109/TR.2016.2604918" target="_blank" >http://dx.doi.org/10.1109/TR.2016.2604918</a>

DOI - Digital Object Identifier

<a href="http://dx.doi.org/10.1109/TR.2016.2604918" target="_blank" >10.1109/TR.2016.2604918</a>

Result language

angličtina

Original language name

Error Mitigation using Approximate Logic Circuits: A Comparison of Probabilistic and Evolutionary Approaches

Original language description

Technology scaling poses an increasing challenge to the reliability of digital circuits. Hardware redundancy solutions, such as triple modular redundancy (TMR), produce very high area overhead, so partial redundancy is often used to reduce the overheads. Approximate logic circuits provide a general framework for optimized mitigation of errors arising from a broad class of failure mechanisms, including transient, intermittent, and permanent failures. However, generating an optimal redundant logic circuit that is able to mask the faults with the highest probability while minimizing the area overheads is a challenging problem. In this study, we propose and compare two new approaches to generate approximate logic circuits to be used in a TMR schema. The probabilistic approach approximates a circuit in a greedy manner based on a probabilistic estimation of the error. The evolutionary approach can provide radically different solutions that are hard to reach by other methods. By combining these two approaches, the solution space can be explored in depth. Experimental results demonstrate that the evolutionary approach can produce better solutions, but the probabilistic approach is close. On the other hand, these approaches provide much better scalability than other existing partial redundancy techniques.

Czech name

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Czech description

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Type

J_imp - Article in a specialist periodical, which is included in the Web of Science database

CEP classification

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OECD FORD branch

20206 - Computer hardware and architecture

Project

Result was created during the realization of more than one project. More information in the Projects tab.

Continuities

P - Projekt vyzkumu a vyvoje financovany z verejnych zdroju (s odkazem do CEP)

Publication year

2016

Confidentiality

S - Úplné a pravdivé údaje o projektu nepodléhají ochraně podle zvláštních právních předpisů

Name of the periodical

IEEE TRANSACTIONS ON RELIABILITY

ISSN

0018-9529

e-ISSN

1558-1721

Volume of the periodical

65

Issue of the periodical within the volume

4

Country of publishing house

US - UNITED STATES

Number of pages

13

Pages from-to

1871-1883

UT code for WoS article

000391284600019

EID of the result in the Scopus database

2-s2.0-84990841014