Acceleration of Feature Extraction for Real-Time Analysis of Encrypted Network Traffic
The result's identifiers
Result code in IS VaVaI
<a href="https://www.isvavai.cz/riv?ss=detail&h=RIV%2F00216305%3A26230%2F19%3APU132971" target="_blank" >RIV/00216305:26230/19:PU132971 - isvavai.cz</a>
Result on the web
<a href="http://dx.doi.org/10.1109/DDECS.2019.8724658" target="_blank" >http://dx.doi.org/10.1109/DDECS.2019.8724658</a>
DOI - Digital Object Identifier
<a href="http://dx.doi.org/10.1109/DDECS.2019.8724658" target="_blank" >10.1109/DDECS.2019.8724658</a>
Alternative languages
Result language
angličtina
Original language name
Acceleration of Feature Extraction for Real-Time Analysis of Encrypted Network Traffic
Original language description
With the growing amount of encrypted network traffic, it is important to have tools for the analysis and classification of encrypted network data. Encrypted network traffic is usually analysed by statistical methods because Deep Packet Inspection or pattern matching is not applicable. However, the statistical methods are usually designed to work offline on already captured network traffic. For real-time analysis, hardware acceleration is needed to achieve wire-speed 10 Gbps throughput. Therefore, we focus on real-time monitoring of encrypted network traffic and propose a new acceleration method to extract features from encrypted network data. Approximate computing is used to speed up the computation of entropy for the input data stream and to reduce FPGA logic utilization. As can be seen in the results, the precision of classification has decreased only by 0.1 to 0.2. Moreover, proposed hardware architecture has very low FPGA logic utilization and can operate on high frequency.
Czech name
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Czech description
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Classification
Type
D - Article in proceedings
CEP classification
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OECD FORD branch
10201 - Computer sciences, information science, bioinformathics (hardware development to be 2.2, social aspect to be 5.8)
Result continuities
Project
<a href="/en/project/VI20152019001" target="_blank" >VI20152019001: Smart Application Aware Embedded Probes</a><br>
Continuities
P - Projekt vyzkumu a vyvoje financovany z verejnych zdroju (s odkazem do CEP)<br>S - Specificky vyzkum na vysokych skolach
Others
Publication year
2019
Confidentiality
S - Úplné a pravdivé údaje o projektu nepodléhají ochraně podle zvláštních právních předpisů
Data specific for result type
Article name in the collection
Proceedings - 2019 22nd International Symposium on Design and Diagnostics of Electronic Circuits and Systems, DDECS 2019
ISBN
978-1-7281-0073-9
ISSN
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e-ISSN
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Number of pages
6
Pages from-to
1-6
Publisher name
Institute of Electrical and Electronics Engineers
Place of publication
Cluj-Napoca
Event location
Cluj-Napoca
Event date
Apr 24, 2019
Type of event by nationality
WRD - Celosvětová akce
UT code for WoS article
000492839800022