Reliability Analysis of Reconfiguration Controller for FPGA-Based Fault Tolerant Systems: Case Study

Result code in IS VaVaI
<a href="https://www.isvavai.cz/riv?ss=detail&h=RIV%2F00216305%3A26230%2F20%3APU138607" target="_blank" >RIV/00216305:26230/20:PU138607 - isvavai.cz</a>
Result on the web
<a href="https://www.fit.vut.cz/research/publication/12101/" target="_blank" >https://www.fit.vut.cz/research/publication/12101/</a>
DOI - Digital Object Identifier
<a href="http://dx.doi.org/10.1109/VLSI-DAT49148.2020.9196269" target="_blank" >10.1109/VLSI-DAT49148.2020.9196269</a>

Result language
angličtina
Original language name
Reliability Analysis of Reconfiguration Controller for FPGA-Based Fault Tolerant Systems: Case Study
Original language description
This paper deals with a reliability analysis of a reconfiguration controller which can be a component of a fault-tolerant control system. This controller is designed for an FPGA to be capable of using partial dynamic reconfiguration of the FPGA to mitigate potential faults in the FPGAs configuration memory. These faults, which are called SEUs, can be induced by radiation effects. Therefore, fault tolerance measurement or estimation is very important for designing circuits for critical environments. Thus, the reliability of the reconfiguration controller itself is significant; therefore the Fault Tolerance ESTimation (FT-EST) framework is used for reliability evaluation, which is procured by the discovery of a number of critical configuration bits. Two approaches are used and compared: evaluations of used LUT only, and evaluations of all configuration bits. We ascertained a 20x reduction in time consumption at the expense of a proportional decrease in the amount of critical configuration bits discovered. The obtained results are nearly equivalent.
Czech name
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Czech description
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Project
Result was created during the realization of more than one project. More information in the Projects tab.
Continuities
P - Projekt vyzkumu a vyvoje financovany z verejnych zdroju (s odkazem do CEP)<br>S - Specificky vyzkum na vysokych skolach

Publication year
2020
Confidentiality
S - Úplné a pravdivé údaje o projektu nepodléhají ochraně podle zvláštních právních předpisů

Article name in the collection
2020 International Symposium on VLSI Design, Automation, and Test (VLSI-DAT) : proceedings of technical papers
ISBN
978-1-7281-6083-2
ISSN
—
e-ISSN
—
Number of pages
4
Pages from-to
121-124
Publisher name
IEEE Computer Society
Place of publication
Hsinchu
Event location
Ambassador Hotel, Hsinchu, Taiwan
Event date
Aug 10, 2020
Type of event by nationality
WRD - Celosvětová akce
UT code for WoS article
000612045400011

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