Delay-aware evolutionary optimization of digital circuits

Result code in IS VaVaI

<a href="https://www.isvavai.cz/riv?ss=detail&h=RIV%2F00216305%3A26230%2F22%3APU144733" target="_blank" >RIV/00216305:26230/22:PU144733 - isvavai.cz</a>

Result on the web

<a href="http://dx.doi.org/10.1109/ISVLSI54635.2022.00045" target="_blank" >http://dx.doi.org/10.1109/ISVLSI54635.2022.00045</a>

DOI - Digital Object Identifier

<a href="http://dx.doi.org/10.1109/ISVLSI54635.2022.00045" target="_blank" >10.1109/ISVLSI54635.2022.00045</a>

Result language

angličtina

Original language name

Delay-aware evolutionary optimization of digital circuits

Original language description

In the recent years, machine learning techniques have successfully been applied in various areas of digital circuit design including logic synthesis. Evolutionary resynthesis, among others, represents one of the machine learning approaches. This technique is based on local iterative optimization of parts of the original circuit. Even though the local optimization could be inefficient compared to the optimization conducted on the whole circuits, it has been shown that the resynthesis performs extremely well. It produces more compact solutions compared to the state-of-the art synthesis methods. In addition, it scales significantly better compared to the evolutionary optimization performed at the level of the original circuit. The previous methods have been focused solely on the optimization of the number of gates. In this paper, we analyse how the local optimization affects the delay of the resulting circuits and based on that, we propose a modified approach that considers the delay in the course of the optimization process. The proposed modification enables to maintain the delay of the optimized circuit at a reasonable level without a significant overhead. The evaluation conducted on a set of non-trivial highly optimized benchmark circuits representing various real-world circuits demonstrated that the proposed method is able to remove a significant number of gates while preserving the delay within the requested bounds.

Czech name

—

Czech description

—

Type

D - Article in proceedings

CEP classification

—

OECD FORD branch

10201 - Computer sciences, information science, bioinformathics (hardware development to be 2.2, social aspect to be 5.8)

Project

<a href="/en/project/GA22-02067S" target="_blank" >GA22-02067S: AppNeCo: Approximate Neurocomputing</a><br>

Continuities

P - Projekt vyzkumu a vyvoje financovany z verejnych zdroju (s odkazem do CEP)

Publication year

2022

Confidentiality

S - Úplné a pravdivé údaje o projektu nepodléhají ochraně podle zvláštních právních předpisů

Article name in the collection

Proceedings of IEEE Computer Society Annual Symposium on VLSI, ISVLSI

ISBN

978-1-6654-6605-9

ISSN

—

e-ISSN

—

Number of pages

6

Pages from-to

188-193

Publisher name

IEEE Computer Society

Place of publication

Nicosia, Cyprus

Event location

Kypr

Event date

Jul 4, 2022

Type of event by nationality

WRD - Celosvětová akce

UT code for WoS article

000886230500032