The Fault-tolerant Single-FPGA Systems with a Self-repair Reconfiguration Controller

Result code in IS VaVaI

<a href="https://www.isvavai.cz/riv?ss=detail&h=RIV%2F00216305%3A26230%2F23%3APU149351" target="_blank" >RIV/00216305:26230/23:PU149351 - isvavai.cz</a>

Result on the web

<a href="https://www.fit.vut.cz/research/publication/12822/" target="_blank" >https://www.fit.vut.cz/research/publication/12822/</a>

DOI - Digital Object Identifier

<a href="http://dx.doi.org/10.1109/LASCAS56464.2023.10108372" target="_blank" >10.1109/LASCAS56464.2023.10108372</a>

Result language

angličtina

Original language name

The Fault-tolerant Single-FPGA Systems with a Self-repair Reconfiguration Controller

Original language description

Fault tolerance in electronic systems is essential in harsh environments such as space. However, FPGAs that can be used to accelerate various computations are prone to configuration memory failures that determine their function. Repairing these failures is essential to increase system resilience. For this purpose, the partial dynamic reconfiguration controller is necessary. To design a comprehensive system inside one FPGA, we force the controller to be on the same FPGA with a payload circuit. We create and thoroughly test a new reconfiguration controller to increase the system's resiliency with the ability to repair itself during its own operation. For this purpose, the FPGA controller is in coarse-grained triple modular redundancy to be able to recover despite the failure of any of its modules. The proposed controller has been tested to increase the resilience of circuits from a set of benchmark circuits. The entire system with the controller was evaluated on an actual FPGA, where faults were injected directly into the configuration memory of this FPGA. Reliability parameters are measured by a platform designed for this purpose, partly directly on the tested FPGA. As we can see from the results, the mean time to failure has been increased by up to 69% compared to a system equipped with only triple modular redundancy with a reasonable amount of hardware resources. The competitive solution brings only a 42% improvement in resilience with the same parameters.

Czech name

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Czech description

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Type

D - Article in proceedings

CEP classification

—

OECD FORD branch

20206 - Computer hardware and architecture

Project

—

Continuities

S - Specificky vyzkum na vysokych skolach

Publication year

2023

Confidentiality

S - Úplné a pravdivé údaje o projektu nepodléhají ochraně podle zvláštních právních předpisů

Article name in the collection

LASCAS 2023 - 14th IEEE Latin American Symposium on Circuits and Systems, Proceedings

ISBN

978-1-6654-5705-7

ISSN

—

e-ISSN

—

Number of pages

4

Pages from-to

104-107

Publisher name

Institute of Electrical and Electronics Engineers

Place of publication

Quito

Event location

QUITO, ECUADOR

Event date

Feb 28, 2023

Type of event by nationality

WRD - Celosvětová akce

UT code for WoS article

000990483600026