Xel-FPGAs: An End-to-End Automated Exploration Framework for Approximate Accelerators in FPGA-Based Systems

Result code in IS VaVaI

<a href="https://www.isvavai.cz/riv?ss=detail&h=RIV%2F00216305%3A26230%2F23%3APU149414" target="_blank" >RIV/00216305:26230/23:PU149414 - isvavai.cz</a>

Result on the web

<a href="http://dx.doi.org/10.1109/ICCAD57390.2023.10323678" target="_blank" >http://dx.doi.org/10.1109/ICCAD57390.2023.10323678</a>

DOI - Digital Object Identifier

<a href="http://dx.doi.org/10.1109/ICCAD57390.2023.10323678" target="_blank" >10.1109/ICCAD57390.2023.10323678</a>

Result language

angličtina

Original language name

Xel-FPGAs: An End-to-End Automated Exploration Framework for Approximate Accelerators in FPGA-Based Systems

Original language description

Generation and exploration of approximate circuits and accelerators has been a prominent research domain to achieve energy-efficiency and/or performance improvements. This research has predominantly focused on ASICs, while not achieving similar gains when deployed for FPGA-based accelerator systems, due to the inherent architectural differences between the two. In this work, we propose a novel framework, Xel-FPGAs, which leverages statistical or machine learning models to effectively explore the architecture-space of state-of-the-art ASIC-based approximate circuits to cater them for FPGA-based systems given a simple RTL description of the target application. We have also evaluated the scalability of our framework on a multi-stage application using a hierarchical search strategy. The Xel-FPGAs framework is capable of reducing the exploration time by up to 95%, when compared to the default synthesis, place, and route approaches, while identifying an improved set of Pareto-optimal designs for a given application, when compared to the state-of-the-art. The complete framework is open-source and available online at https://github.com/ehw-fit/xel-fpgas.

Czech name

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Czech description

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Type

D - Article in proceedings

CEP classification

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OECD FORD branch

10201 - Computer sciences, information science, bioinformathics (hardware development to be 2.2, social aspect to be 5.8)

Project

<a href="/en/project/GA21-13001S" target="_blank" >GA21-13001S: Automated design of hardware accelerators for resource-aware machine learning</a><br>

Continuities

P - Projekt vyzkumu a vyvoje financovany z verejnych zdroju (s odkazem do CEP)

Publication year

2023

Confidentiality

S - Úplné a pravdivé údaje o projektu nepodléhají ochraně podle zvláštních právních předpisů

Article name in the collection

2023 IEEE/ACM International Conference on Computer Aided Design (ICCAD)

ISBN

979-8-3503-1559-2

ISSN

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e-ISSN

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Number of pages

9

Pages from-to

1-9

Publisher name

Institute of Electrical and Electronics Engineers

Place of publication

San Francisco

Event location

San Francisco, California, USA

Event date

Oct 29, 2023

Type of event by nationality

WRD - Celosvětová akce

UT code for WoS article

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