ApproxFPGAs: Embracing ASIC-based Approximate Arithmetic Components for FPGA-Based Systems
The result's identifiers
Result code in IS VaVaI
<a href="https://www.isvavai.cz/riv?ss=detail&h=RIV%2F00216305%3A26230%2F20%3APU138612" target="_blank" >RIV/00216305:26230/20:PU138612 - isvavai.cz</a>
Result on the web
<a href="https://arxiv.org/abs/2004.10502" target="_blank" >https://arxiv.org/abs/2004.10502</a>
DOI - Digital Object Identifier
<a href="http://dx.doi.org/10.1109/DAC18072.2020.9218533" target="_blank" >10.1109/DAC18072.2020.9218533</a>
Alternative languages
Result language
angličtina
Original language name
ApproxFPGAs: Embracing ASIC-based Approximate Arithmetic Components for FPGA-Based Systems
Original language description
There has been abundant research on the development of Approximate Circuits (ACs) for ASICs. However, previous studies have illustrated that ASIC-based ACs offer asymmetrical gains in FPGA-based accelerators. Therefore, an AC that might be pareto-optimal for ASICs might not be pareto-optimal for FPGAs. In this work, we present the ApproxFPGAs methodology that uses machine learning models to reduce the exploration time for analyzing the state-of-the-art ASIC-based ACs to determine the set of pareto-optimal FPGA-based ACs. We also perform a case-study to illustrate the benefits obtained by deploying these pareto-optimal FPGA-ACs in a state-of-the-art automation framework to systematically generate pareto-optimal approximate accelerators that can be deployed in FPGA-based systems to achieve high performance or low-power consumption.
Czech name
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Czech description
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Classification
Type
D - Article in proceedings
CEP classification
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OECD FORD branch
10201 - Computer sciences, information science, bioinformathics (hardware development to be 2.2, social aspect to be 5.8)
Result continuities
Project
<a href="/en/project/GA19-10137S" target="_blank" >GA19-10137S: Designing and exploiting libraries of approximate circuits</a><br>
Continuities
P - Projekt vyzkumu a vyvoje financovany z verejnych zdroju (s odkazem do CEP)
Others
Publication year
2020
Confidentiality
S - Úplné a pravdivé údaje o projektu nepodléhají ochraně podle zvláštních právních předpisů
Data specific for result type
Article name in the collection
2020 57th ACM/IEEE Design Automation Conference (DAC)
ISBN
978-1-4503-6725-7
ISSN
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e-ISSN
—
Number of pages
6
Pages from-to
1-6
Publisher name
Institute of Electrical and Electronics Engineers
Place of publication
San Francisco
Event location
San Francisco, CA
Event date
Jul 19, 2020
Type of event by nationality
WRD - Celosvětová akce
UT code for WoS article
000628528400045